1 /* $Id: dvma.h,v 1.4 1999/03/27 20:23:41 tsbogend Exp $
2 * include/asm-m68k/dma.h
3 *
4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
5 *
6 * Hacked to fit Sun3x needs by Thomas Bogendoerfer
7 */
8
9 #ifndef __M68K_DVMA_H
10 #define __M68K_DVMA_H
11
12 #include <linux/config.h>
13
14 #ifdef CONFIG_SUN3
15 /* sun3 dvma page support */
16
17 #define DVMA_RESERVED_PMEGS 2 /* 256k of dvma */
18
19 /* memory and pmegs potentially reserved for dvma */
20 #define DVMA_PMEG_START 10
21 #define DVMA_PMEG_END 16
22 #define DVMA_START 0xff00000
23 #define DVMA_END 0xffe0000
24 #define DVMA_SIZE (DVMA_END-DVMA_START)
25
26 /* empirical kludge -- dvma regions only seem to work right on 0x10000
27 byte boundries */
28 #define DVMA_REGION_SIZE 0x10000
29 #define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
30 ~(DVMA_REGION_SIZE-1))
31
32
33 /* virt <-> phys conversions */
34 #define sun3_dvma_vtop(x) ((unsigned long)(x) & 0xffffff)
35 #define sun3_dvma_ptov(x) ((unsigned long)(x) | 0xf000000)
36
37 extern void sun3_dvma_init(void);
38 extern void *sun3_dvma_malloc(int len);
39 #else /* Sun3x */
40
41 /* Structure to describe the current status of DMA registers on the Sparc */
42 struct sparc_dma_registers {
43 __volatile__ unsigned long cond_reg; /* DMA condition register */
44 __volatile__ unsigned long st_addr; /* Start address of this transfer */
45 __volatile__ unsigned long cnt; /* How many bytes to transfer */
46 __volatile__ unsigned long dma_test; /* DMA test register */
47 };
48
49 /* DVMA chip revisions */
50 enum dvma_rev {
51 dvmarev0,
52 dvmaesc1,
53 dvmarev1,
54 dvmarev2,
55 dvmarev3,
56 dvmarevplus,
57 dvmahme
58 };
59
60 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
61
62 /* Linux DMA information structure, filled during probe. */
63 struct Linux_SBus_DMA {
64 struct Linux_SBus_DMA *next;
65 struct linux_sbus_device *SBus_dev;
66 struct sparc_dma_registers *regs;
67
68 /* Status, misc info */
69 int node; /* Prom node for this DMA device */
70 int running; /* Are we doing DMA now? */
71 int allocated; /* Are we "owned" by anyone yet? */
72
73 /* Transfer information. */
74 unsigned long addr; /* Start address of current transfer */
75 int nbytes; /* Size of current transfer */
76 int realbytes; /* For splitting up large transfers, etc. */
77
78 /* DMA revision */
79 enum dvma_rev revision;
80 };
81
82 extern struct Linux_SBus_DMA *dma_chain;
83
84 /* Broken hardware... */
85 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
86 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
87
88 /* Fields in the cond_reg register */
89 /* First, the version identification bits */
90 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
91 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
92 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
93 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
94 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
95 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
96 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
97
98 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
99 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
100 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
101 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
102 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
103 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
104 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
105 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
106 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
107 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
108 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
109 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
110 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
111 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
112 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
113 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
114 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
115 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
116 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
117 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
118 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
119 #define DMA_E_BURST8 0x00040000 /* ENET: SBUS r/w burst size */
120 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
121 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
122 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
123 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
124 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
125 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
126 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
127 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
128 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
129 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
130 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
131 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
132 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
133 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
134 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
135
136 /* Values describing the burst-size property from the PROM */
137 #define DMA_BURST1 0x01
138 #define DMA_BURST2 0x02
139 #define DMA_BURST4 0x04
140 #define DMA_BURST8 0x08
141 #define DMA_BURST16 0x10
142 #define DMA_BURST32 0x20
143 #define DMA_BURST64 0x40
144 #define DMA_BURSTBITS 0x7f
145
146 /* Determine highest possible final transfer address given a base */
147 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
148
149 /* Yes, I hack a lot of elisp in my spare time... */
150 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
151 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
152 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
153 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
154 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
155 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
156 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
157 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
158 #define DMA_BEGINDMA_W(regs) \
159 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
160 #define DMA_BEGINDMA_R(regs) \
161 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
162
163 /* For certain DMA chips, we need to disable ints upon irq entry
164 * and turn them back on when we are done. So in any ESP interrupt
165 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
166 * when leaving the handler. You have been warned...
167 */
168 #define DMA_IRQ_ENTRY(dma, dregs) do { \
169 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
170 } while (0)
171
172 #define DMA_IRQ_EXIT(dma, dregs) do { \
173 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
174 } while(0)
175
176 /* Reset the friggin' thing... */
177 #define DMA_RESET(dma) do { \
178 struct sparc_dma_registers *regs = dma->regs; \
179 /* Let the current FIFO drain itself */ \
180 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
181 /* Reset the logic */ \
182 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
183 __delay(400); /* let the bits set ;) */ \
184 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
185 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
186 /* Enable FAST transfers if available */ \
187 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
188 dma->running = 0; \
189 } while(0)
190
191 extern unsigned long dvma_alloc (unsigned long, unsigned long);
192 extern void dvma_free (unsigned long, unsigned long);
193 #endif /* !CONFIG_SUN3 */
194 #endif /* !(__M68K_DVMA_H) */
195
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