1 /*
2 * Q40 master Chip Control
3 * RTC stuff merged for compactnes..
4 */
5
6 #ifndef _Q40_MASTER_H
7 #define _Q40_MASTER_H
8
9 #include <asm/io.h>
10
11
12 #define q40_master_addr 0xff000000
13 #define q40_rtc_addr 0xff021ffc
14
15 #define IIRQ_REG 0x0 /* internal IRQ reg */
16 #define EIRQ_REG 0x4 /* external ... */
17 #define KEYCODE_REG 0x1c /* value of received scancode */
18 #define DISPLAY_CONTROL_REG 0x18
19 #define FRAME_CLEAR_REG 0x24
20
21 #define INTERRUPT_REG IIRQ_REG /* "native" ints */
22 #define KEY_IRQ_ENABLE_REG 0x08 /**/
23 #define KEYBOARD_UNLOCK_REG 0x20 /* clear kb int */
24
25 #define SAMPLE_ENABLE_REG 0x14 /* generate SAMPLE ints */
26 #define SAMPLE_RATE_REG 0x2c
27 #define SAMPLE_CLEAR_REG 0x28
28 #define SAMPLE_LOW 0x00
29 #define SAMPLE_HIGH 0x01
30
31 #define FRAME_RATE_REG 0x38 /* generate FRAME ints at 200 HZ rate */
32
33 #if 0
34 #define SER_ENABLE_REG 0x0c /* allow serial ints to be generated */
35 #endif
36 #define EXT_ENABLE_REG 0x10 /* ... rest of the ISA ints ... */
37
38 #if 0
39 #define master_inb(_reg_) (*(((unsigned char *)q40_master_addr)+_reg_))
40 #define master_outb(_b_,_reg_) (*(((unsigned char *)q40_master_addr)+_reg_)=(_b_))
41 #else
42 #define master_inb(_reg_) native_inb((unsigned char *)q40_master_addr+_reg_)
43 #define master_outb(_b_,_reg_) native_outb(_b_,(unsigned char *)q40_master_addr+_reg_)
44 #endif
45
46 /* define some Q40 specific ints */
47 #include "q40ints.h"
48
49 /* RTC defines */
50
51 #define Q40_RTC_BASE (q40_rtc_addr)
52
53 #define RTC_YEAR (*(unsigned char *)(Q40_RTC_BASE+0))
54 #define RTC_MNTH (*(unsigned char *)(Q40_RTC_BASE-4))
55 #define RTC_DATE (*(unsigned char *)(Q40_RTC_BASE-8))
56 #define RTC_DOW (*(unsigned char *)(Q40_RTC_BASE-12))
57 #define RTC_HOUR (*(unsigned char *)(Q40_RTC_BASE-16))
58 #define RTC_MINS (*(unsigned char *)(Q40_RTC_BASE-20))
59 #define RTC_SECS (*(unsigned char *)(Q40_RTC_BASE-24))
60 #define RTC_CTRL (*(unsigned char *)(Q40_RTC_BASE-28))
61
62
63 /* some control bits */
64 #define RTC_READ 64 /* prepare for reading */
65 #define RTC_WRITE 128
66
67
68 /* misc defs */
69 #define DAC_LEFT ((unsigned char *)0xff008000)
70 #define DAC_RIGHT ((unsigned char *)0xff008004)
71
72 #endif /* _Q40_MASTER_H */
73
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