1 /*
2 * include/asm-mips/asm.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
9 *
10 * Some useful macros for MIPS assembler code
11 *
12 * Some of the routines below contain useless nops that will be optimized
13 * away by gas in -O mode. These nops are however required to fill delay
14 * slots in noreorder mode.
15 */
16 #ifndef __ASM_ASM_H
17 #define __ASM_ASM_H
18
19 #include <asm/sgidefs.h>
20
21 #ifndef CAT
22 #ifdef __STDC__
23 #define __CAT(str1,str2) str1##str2
24 #else
25 #define __CAT(str1,str2) str1/**/str2
26 #endif
27 #define CAT(str1,str2) __CAT(str1,str2)
28 #endif
29
30 /*
31 * Macros to handle different pointer/register sizes for 32/64-bit code
32 *
33 * 64 bit address space isn't used yet, so we may use the R3000 32 bit
34 * defines for now.
35 */
36 #define PTR .word
37 #define PTRSIZE 4
38 #define PTRLOG 2
39
40 /*
41 * PIC specific declarations
42 * Not used for the kernel but here seems to be the right place.
43 */
44 #ifdef __PIC__
45 #define CPRESTORE(register) \
46 .cprestore register
47 #define CPADD(register) \
48 .cpadd register
49 #define CPLOAD(register) \
50 .cpload register
51 #else
52 #define CPRESTORE(register)
53 #define CPADD(register)
54 #define CPLOAD(register)
55 #endif
56
57 /*
58 * LEAF - declare leaf routine
59 */
60 #define LEAF(symbol) \
61 .globl symbol; \
62 .align 2; \
63 .type symbol,@function; \
64 .ent symbol,0; \
65 symbol: .frame sp,0,ra
66
67 /*
68 * NESTED - declare nested routine entry point
69 */
70 #define NESTED(symbol, framesize, rpc) \
71 .globl symbol; \
72 .align 2; \
73 .type symbol,@function; \
74 .ent symbol,0; \
75 symbol: .frame sp, framesize, rpc
76
77 /*
78 * END - mark end of function
79 */
80 #define END(function) \
81 .end function; \
82 .size function,.-function
83
84 /*
85 * EXPORT - export definition of symbol
86 */
87 #define EXPORT(symbol) \
88 .globl symbol; \
89 symbol:
90
91 /*
92 * ABS - export absolute symbol
93 */
94 #define ABS(symbol,value) \
95 .globl symbol; \
96 symbol = value
97
98 #define PANIC(msg) \
99 .set push; \
100 .set reorder; \
101 la a0,8f; \
102 jal panic; \
103 9: b 9b; \
104 .set pop; \
105 TEXT(msg)
106
107 /*
108 * Print formated string
109 */
110 #define PRINT(string) \
111 .set push; \
112 .set reorder; \
113 la a0,8f; \
114 jal printk; \
115 .set pop; \
116 TEXT(string)
117
118 #define TEXT(msg) \
119 .data; \
120 8: .asciiz msg; \
121 .previous;
122
123 /*
124 * Build text tables
125 */
126 #define TTABLE(string) \
127 .text; \
128 .word 1f; \
129 .previous; \
130 .data; \
131 1: .asciz string; \
132 .previous
133
134 /*
135 * MIPS IV pref instruction.
136 * Use with .set noreorder only!
137 *
138 * MIPS IV implementations are free to treat this as a nop. The R5000
139 * is one of them. So we should have an option not to use this instruction.
140 */
141 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
142 #define PREF(hint,addr) \
143 pref hint,addr
144 #define PREFX(hint,addr) \
145 prefx hint,addr
146 #else
147 #define PREF
148 #define PREFX
149 #endif
150
151 /*
152 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
153 */
154 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
155 #define MOVN(rd,rs,rt) \
156 .set push; \
157 .set noreorder; \
158 beqz rt,9f; \
159 move rd,rs; \
160 .set pop; \
161 9:
162 #define MOVZ(rd,rs,rt) \
163 .set push; \
164 .set noreorder; \
165 bnez rt,9f; \
166 move rd,rt; \
167 .set pop; \
168 9:
169 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
170 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
171 #define MOVN(rd,rs,rt) \
172 .set push; \
173 .set noreorder; \
174 bnezl rt,9f; \
175 move rd,rs; \
176 .set pop; \
177 9:
178 #define MOVZ(rd,rs,rt) \
179 .set push; \
180 .set noreorder; \
181 beqzl rt,9f; \
182 movz rd,rs; \
183 .set pop; \
184 9:
185 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
186 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
187 #define MOVN(rd,rs,rt) \
188 movn rd,rs,rt
189 #define MOVZ(rd,rs,rt) \
190 movz rd,rs,rt
191 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
192
193 /*
194 * Stack alignment
195 */
196 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
197 #define ALSZ 7
198 #define ALMASK ~7
199 #endif
200 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
201 (_MIPS_ISA == _MIPS_ISA_MIPS5)
202 #define ALSZ 15
203 #define ALMASK ~15
204 #endif
205
206 /*
207 * Size of a register
208 */
209 #ifdef __mips64
210 #define SZREG 8
211 #else
212 #define SZREG 4
213 #endif
214
215 /*
216 * Use the following macros in assemblercode to load/store registers,
217 * pointers etc.
218 */
219 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
220 #define REG_S sw
221 #define REG_L lw
222 #define PTR_SUBU subu
223 #define PTR_ADDU addu
224 #endif
225 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
226 (_MIPS_ISA == _MIPS_ISA_MIPS5)
227 #define REG_S sd
228 #define REG_L ld
229 /* We still live in a 32 bit address space ... */
230 #define PTR_SUBU subu
231 #define PTR_ADDU addu
232 #endif
233
234 /*
235 * How to add/sub/load/store/shift C int variables.
236 */
237 #if (_MIPS_SZINT == 32)
238 #define INT_ADD add
239 #define INT_ADDI addi
240 #define INT_ADDU addu
241 #define INT_ADDIU addiu
242 #define INT_SUB add
243 #define INT_SUBI subi
244 #define INT_SUBU subu
245 #define INT_SUBIU subu
246 #define INT_L lw
247 #define INT_S sw
248 #define LONG_SLL sll
249 #define LONG_SLLV sllv
250 #define LONG_SRL srl
251 #define LONG_SRLV srlv
252 #define LONG_SRA sra
253 #define LONG_SRAV srav
254 #endif
255
256 #if (_MIPS_SZINT == 64)
257 #define INT_ADD dadd
258 #define INT_ADDI daddi
259 #define INT_ADDU daddu
260 #define INT_ADDIU daddiu
261 #define INT_SUB dadd
262 #define INT_SUBI dsubi
263 #define INT_SUBU dsubu
264 #define INT_SUBIU dsubu
265 #define INT_L ld
266 #define INT_S sd
267 #define LONG_SLL dsll
268 #define LONG_SLLV dsllv
269 #define LONG_SRL dsrl
270 #define LONG_SRLV dsrlv
271 #define LONG_SRA dsra
272 #define LONG_SRAV dsrav
273 #endif
274
275 /*
276 * How to add/sub/load/store/shift C long variables.
277 */
278 #if (_MIPS_SZLONG == 32)
279 #define LONG_ADD add
280 #define LONG_ADDI addi
281 #define LONG_ADDU addu
282 #define LONG_ADDIU addiu
283 #define LONG_SUB add
284 #define LONG_SUBI subi
285 #define LONG_SUBU subu
286 #define LONG_SUBIU subu
287 #define LONG_L lw
288 #define LONG_S sw
289 #define LONG_SLL sll
290 #define LONG_SLLV sllv
291 #define LONG_SRL srl
292 #define LONG_SRLV srlv
293 #define LONG_SRA sra
294 #define LONG_SRAV srav
295 #endif
296
297 #if (_MIPS_SZLONG == 64)
298 #define LONG_ADD dadd
299 #define LONG_ADDI daddi
300 #define LONG_ADDU daddu
301 #define LONG_ADDIU daddiu
302 #define LONG_SUB dadd
303 #define LONG_SUBI dsubi
304 #define LONG_SUBU dsubu
305 #define LONG_SUBIU dsubu
306 #define LONG_L ld
307 #define LONG_S sd
308 #define LONG_SLL dsll
309 #define LONG_SLLV dsllv
310 #define LONG_SRL dsrl
311 #define LONG_SRLV dsrlv
312 #define LONG_SRA dsra
313 #define LONG_SRAV dsrav
314 #endif
315
316 /*
317 * How to add/sub/load/store/shift pointers.
318 */
319 #if (_MIPS_SZLONG == 32)
320 #define PTR_ADD add
321 #define PTR_ADDI addi
322 #define PTR_ADDU addu
323 #define PTR_ADDIU addiu
324 #define PTR_SUB add
325 #define PTR_SUBI subi
326 #define PTR_SUBU subu
327 #define PTR_SUBIU subu
328 #define PTR_L lw
329 #define PTR_S sw
330 #define PTR_SLL sll
331 #define PTR_SLLV sllv
332 #define PTR_SRL srl
333 #define PTR_SRLV srlv
334 #define PTR_SRA sra
335 #define PTR_SRAV srav
336
337 #define PTR_SCALESHIFT 2
338 #endif
339
340 #if (_MIPS_SZLONG == 64)
341 #define PTR_ADD dadd
342 #define PTR_ADDI daddi
343 #define PTR_ADDU daddu
344 #define PTR_ADDIU daddiu
345 #define PTR_SUB dadd
346 #define PTR_SUBI dsubi
347 #define PTR_SUBU dsubu
348 #define PTR_SUBIU dsubu
349 #define PTR_L ld
350 #define PTR_S sd
351 #define PTR_SLL dsll
352 #define PTR_SLLV dsllv
353 #define PTR_SRL dsrl
354 #define PTR_SRLV dsrlv
355 #define PTR_SRA dsra
356 #define PTR_SRAV dsrav
357
358 #define PTR_SCALESHIFT 3
359 #endif
360
361 /*
362 * Some cp0 registers were extended to 64bit for MIPS III.
363 */
364 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
365 #define MFC0 mfc0
366 #define MTC0 mtc0
367 #endif
368 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
369 (_MIPS_ISA == _MIPS_ISA_MIPS5)
370 #define MFC0 dmfc0
371 #define MTC0 dmtc0
372 #endif
373
374 #endif /* __ASM_ASM_H */
375
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