1 /*
2 * asmmacro.h: Assembler macros to make things easier to read.
3 *
4 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
5 * Copyright (C) 1998 Ralf Baechle
6 *
7 * $Id: asmmacro.h,v 1.3 1998/03/27 04:47:58 ralf Exp $
8 */
9 #ifndef __MIPS_ASMMACRO_H
10 #define __MIPS_ASMMACRO_H
11
12 #include <asm/offset.h>
13
14 #define FPU_SAVE_DOUBLE(thread, tmp) \
15 cfc1 tmp, fcr31; \
16 sdc1 $f0, (THREAD_FPU + 0x000)(thread); \
17 sdc1 $f2, (THREAD_FPU + 0x008)(thread); \
18 sdc1 $f4, (THREAD_FPU + 0x010)(thread); \
19 sdc1 $f6, (THREAD_FPU + 0x018)(thread); \
20 sdc1 $f8, (THREAD_FPU + 0x020)(thread); \
21 sdc1 $f10, (THREAD_FPU + 0x028)(thread); \
22 sdc1 $f12, (THREAD_FPU + 0x030)(thread); \
23 sdc1 $f14, (THREAD_FPU + 0x038)(thread); \
24 sdc1 $f16, (THREAD_FPU + 0x040)(thread); \
25 sdc1 $f18, (THREAD_FPU + 0x048)(thread); \
26 sdc1 $f20, (THREAD_FPU + 0x050)(thread); \
27 sdc1 $f22, (THREAD_FPU + 0x058)(thread); \
28 sdc1 $f24, (THREAD_FPU + 0x060)(thread); \
29 sdc1 $f26, (THREAD_FPU + 0x068)(thread); \
30 sdc1 $f28, (THREAD_FPU + 0x070)(thread); \
31 sdc1 $f30, (THREAD_FPU + 0x078)(thread); \
32 sw tmp, (THREAD_FPU + 0x080)(thread)
33
34 #define FPU_SAVE_SINGLE(thread,tmp) \
35 cfc1 tmp, fcr31; \
36 swc1 $f0, (THREAD_FPU + 0x000)(thread); \
37 swc1 $f1, (THREAD_FPU + 0x004)(thread); \
38 swc1 $f2, (THREAD_FPU + 0x008)(thread); \
39 swc1 $f3, (THREAD_FPU + 0x00c)(thread); \
40 swc1 $f4, (THREAD_FPU + 0x010)(thread); \
41 swc1 $f5, (THREAD_FPU + 0x014)(thread); \
42 swc1 $f6, (THREAD_FPU + 0x018)(thread); \
43 swc1 $f7, (THREAD_FPU + 0x01c)(thread); \
44 swc1 $f8, (THREAD_FPU + 0x020)(thread); \
45 swc1 $f9, (THREAD_FPU + 0x024)(thread); \
46 swc1 $f10, (THREAD_FPU + 0x028)(thread); \
47 swc1 $f11, (THREAD_FPU + 0x02c)(thread); \
48 swc1 $f12, (THREAD_FPU + 0x030)(thread); \
49 swc1 $f13, (THREAD_FPU + 0x034)(thread); \
50 swc1 $f14, (THREAD_FPU + 0x038)(thread); \
51 swc1 $f15, (THREAD_FPU + 0x03c)(thread); \
52 swc1 $f16, (THREAD_FPU + 0x040)(thread); \
53 swc1 $f17, (THREAD_FPU + 0x044)(thread); \
54 swc1 $f18, (THREAD_FPU + 0x048)(thread); \
55 swc1 $f19, (THREAD_FPU + 0x04c)(thread); \
56 swc1 $f20, (THREAD_FPU + 0x050)(thread); \
57 swc1 $f21, (THREAD_FPU + 0x054)(thread); \
58 swc1 $f22, (THREAD_FPU + 0x058)(thread); \
59 swc1 $f23, (THREAD_FPU + 0x05c)(thread); \
60 swc1 $f24, (THREAD_FPU + 0x060)(thread); \
61 swc1 $f25, (THREAD_FPU + 0x064)(thread); \
62 swc1 $f26, (THREAD_FPU + 0x068)(thread); \
63 swc1 $f27, (THREAD_FPU + 0x06c)(thread); \
64 swc1 $f28, (THREAD_FPU + 0x070)(thread); \
65 swc1 $f29, (THREAD_FPU + 0x074)(thread); \
66 swc1 $f30, (THREAD_FPU + 0x078)(thread); \
67 swc1 $f31, (THREAD_FPU + 0x07c)(thread); \
68 sw tmp, (THREAD_FPU + 0x080)(thread)
69
70 #define FPU_RESTORE_DOUBLE(thread, tmp) \
71 lw tmp, (THREAD_FPU + 0x080)(thread); \
72 ldc1 $f0, (THREAD_FPU + 0x000)(thread); \
73 ldc1 $f2, (THREAD_FPU + 0x008)(thread); \
74 ldc1 $f4, (THREAD_FPU + 0x010)(thread); \
75 ldc1 $f6, (THREAD_FPU + 0x018)(thread); \
76 ldc1 $f8, (THREAD_FPU + 0x020)(thread); \
77 ldc1 $f10, (THREAD_FPU + 0x028)(thread); \
78 ldc1 $f12, (THREAD_FPU + 0x030)(thread); \
79 ldc1 $f14, (THREAD_FPU + 0x038)(thread); \
80 ldc1 $f16, (THREAD_FPU + 0x040)(thread); \
81 ldc1 $f18, (THREAD_FPU + 0x048)(thread); \
82 ldc1 $f20, (THREAD_FPU + 0x050)(thread); \
83 ldc1 $f22, (THREAD_FPU + 0x058)(thread); \
84 ldc1 $f24, (THREAD_FPU + 0x060)(thread); \
85 ldc1 $f26, (THREAD_FPU + 0x068)(thread); \
86 ldc1 $f28, (THREAD_FPU + 0x070)(thread); \
87 ldc1 $f30, (THREAD_FPU + 0x078)(thread); \
88 ctc1 tmp, fcr31
89
90 #define FPU_RESTORE_SINGLE(thread,tmp) \
91 lw tmp, (THREAD_FPU + 0x080)(thread); \
92 lwc1 $f0, (THREAD_FPU + 0x000)(thread); \
93 lwc1 $f1, (THREAD_FPU + 0x004)(thread); \
94 lwc1 $f2, (THREAD_FPU + 0x008)(thread); \
95 lwc1 $f3, (THREAD_FPU + 0x00c)(thread); \
96 lwc1 $f4, (THREAD_FPU + 0x010)(thread); \
97 lwc1 $f5, (THREAD_FPU + 0x014)(thread); \
98 lwc1 $f6, (THREAD_FPU + 0x018)(thread); \
99 lwc1 $f7, (THREAD_FPU + 0x01c)(thread); \
100 lwc1 $f8, (THREAD_FPU + 0x020)(thread); \
101 lwc1 $f9, (THREAD_FPU + 0x024)(thread); \
102 lwc1 $f10, (THREAD_FPU + 0x028)(thread); \
103 lwc1 $f11, (THREAD_FPU + 0x02c)(thread); \
104 lwc1 $f12, (THREAD_FPU + 0x030)(thread); \
105 lwc1 $f13, (THREAD_FPU + 0x034)(thread); \
106 lwc1 $f14, (THREAD_FPU + 0x038)(thread); \
107 lwc1 $f15, (THREAD_FPU + 0x03c)(thread); \
108 lwc1 $f16, (THREAD_FPU + 0x040)(thread); \
109 lwc1 $f17, (THREAD_FPU + 0x044)(thread); \
110 lwc1 $f18, (THREAD_FPU + 0x048)(thread); \
111 lwc1 $f19, (THREAD_FPU + 0x04c)(thread); \
112 lwc1 $f20, (THREAD_FPU + 0x050)(thread); \
113 lwc1 $f21, (THREAD_FPU + 0x054)(thread); \
114 lwc1 $f22, (THREAD_FPU + 0x058)(thread); \
115 lwc1 $f23, (THREAD_FPU + 0x05c)(thread); \
116 lwc1 $f24, (THREAD_FPU + 0x060)(thread); \
117 lwc1 $f25, (THREAD_FPU + 0x064)(thread); \
118 lwc1 $f26, (THREAD_FPU + 0x068)(thread); \
119 lwc1 $f27, (THREAD_FPU + 0x06c)(thread); \
120 lwc1 $f28, (THREAD_FPU + 0x070)(thread); \
121 lwc1 $f29, (THREAD_FPU + 0x074)(thread); \
122 lwc1 $f30, (THREAD_FPU + 0x078)(thread); \
123 lwc1 $f31, (THREAD_FPU + 0x07c)(thread); \
124 ctc1 tmp, fcr31
125
126 #define CPU_SAVE_NONSCRATCH(thread) \
127 sw s0, THREAD_REG16(thread); \
128 sw s1, THREAD_REG17(thread); \
129 sw s2, THREAD_REG18(thread); \
130 sw s3, THREAD_REG19(thread); \
131 sw s4, THREAD_REG20(thread); \
132 sw s5, THREAD_REG21(thread); \
133 sw s6, THREAD_REG22(thread); \
134 sw s7, THREAD_REG23(thread); \
135 sw sp, THREAD_REG29(thread); \
136 sw fp, THREAD_REG30(thread)
137
138 #define CPU_RESTORE_NONSCRATCH(thread) \
139 lw s0, THREAD_REG16(thread); \
140 lw s1, THREAD_REG17(thread); \
141 lw s2, THREAD_REG18(thread); \
142 lw s3, THREAD_REG19(thread); \
143 lw s4, THREAD_REG20(thread); \
144 lw s5, THREAD_REG21(thread); \
145 lw s6, THREAD_REG22(thread); \
146 lw s7, THREAD_REG23(thread); \
147 lw sp, THREAD_REG29(thread); \
148 lw fp, THREAD_REG30(thread); \
149 lw ra, THREAD_REG31(thread)
150
151 #endif /* !(__MIPS_ASMMACRO_H) */
152
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