1 /*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996 by Ralf Baechle
9 */
10 #ifndef __ASM_MIPS_INST_H
11 #define __ASM_MIPS_INST_H
12
13 /*
14 * Major opcodes; before MIPS IV cop1x was called cop3.
15 */
16 enum major_op {
17 spec_op, bcond_op, j_op, jal_op,
18 beq_op, bne_op, blez_op, bgtz_op,
19 addi_op, addiu_op, slti_op, sltiu_op,
20 andi_op, ori_op, xori_op, lui_op,
21 cop0_op, cop1_op, cop2_op, cop1x_op,
22 beql_op, bnel_op, blezl_op, bgtzl_op,
23 daddi_op, daddiu_op, ldl_op, ldr_op,
24 major_1c_op, major_1d_op, major_1e_op, major_1f_op,
25 lb_op, lh_op, lwl_op, lw_op,
26 lbu_op, lhu_op, lwr_op, lwu_op,
27 sb_op, sh_op, swl_op, sw_op,
28 sdl_op, sdr_op, swr_op, cache_op,
29 ll_op, lwc1_op, lwc2_op, pref_op,
30 lld_op, ldc1_op, ldc2_op, ld_op,
31 sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
32 scd_op, sdc1_op, sdc2_op, sd_op
33 };
34
35 /*
36 * func field of spec opcode.
37 */
38 enum spec_op {
39 sll_op, movc_op, srl_op, sra_op,
40 sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
41 jr_op, jalr_op, movz_op, movn_op,
42 syscall_op, break_op, spim_op, sync_op,
43 mfhi_op, mthi_op, mflo_op, mtlo_op,
44 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
45 mult_op, multu_op, div_op, divu_op,
46 dmult_op, dmultu_op, ddiv_op, ddivu_op,
47 add_op, addu_op, sub_op, subu_op,
48 and_op, or_op, xor_op, nor_op,
49 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
50 dadd_op, daddu_op, dsub_op, dsubu_op,
51 tge_op, tgeu_op, tlt_op, tltu_op,
52 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
53 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
54 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
55 };
56
57 /*
58 * rt field of bcond opcodes.
59 */
60 enum rt_op {
61 bltz_op, bgez_op, bltzl_op, bgezl_op,
62 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
63 tgei_op, tgeiu_op, tlti_op, tltiu_op,
64 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
65 bltzal_op, bgezal_op, bltzall_op, bgezall_op
66 /*
67 * The others (0x14 - 0x1f) are unused.
68 */
69 };
70
71 /*
72 * rs field of cop opcodes.
73 */
74 enum cop_op {
75 mfc_op = 0x00, dmfc_op = 0x01,
76 cfc_op = 0x02, mtc_op = 0x04,
77 dmtc_op = 0x05, ctc_op = 0x06,
78 bc_op = 0x08, cop_op = 0x10,
79 copm_op = 0x18
80 };
81
82 /*
83 * func field of cop0 coi opcodes.
84 */
85 enum cop0_coi_func {
86 tlbr_op = 0x01, tlbwi_op = 0x02,
87 tlbwr_op = 0x06, tlbp_op = 0x08,
88 rfe_op = 0x10, eret_op = 0x18
89 };
90
91 /*
92 * func field of cop0 com opcodes.
93 */
94 enum cop0_com_func {
95 tlbr1_op = 0x01, tlbw_op = 0x02,
96 tlbp1_op = 0x08, dctr_op = 0x09,
97 dctw_op = 0x0a
98 };
99
100 /*
101 * fmt field of cop1 opcodes.
102 */
103 enum cop1_fmt {
104 s_fmt, d_fmt, e_fmt, q_fmt,
105 w_fmt, l_fmt
106 };
107
108 /*
109 * func field of cop1 instructions using d, s or w format.
110 */
111 enum cop1_sdw_func {
112 fadd_op = 0x00, fsub_op = 0x01,
113 fmul_op = 0x02, fdiv_op = 0x03,
114 fsqrt_op = 0x04, fabs_op = 0x05,
115 fmov_op = 0x06, fneg_op = 0x07,
116 froundl_op = 0x08, ftruncl_op = 0x09,
117 fceill_op = 0x0a, ffloorl_op = 0x0b,
118 fround_op = 0x0c, ftrunc_op = 0x0d,
119 fceil_op = 0x0e, ffloor_op = 0x0f,
120 fmovc_op = 0x11, fmovz_op = 0x12,
121 fmovn_op = 0x13, frecip_op = 0x15,
122 frsqrt_op = 0x16, fcvts_op = 0x20,
123 fcvtd_op = 0x21, fcvte_op = 0x22,
124 fcvtw_op = 0x24, fcvtl_op = 0x25,
125 fcmp_op = 0x30
126 };
127
128 /*
129 * func field of cop1x opcodes (MIPS IV).
130 */
131 enum cop1x_func {
132 lwxc1_op = 0x00, ldxc1_op = 0x01,
133 pfetch_op = 0x07, swxc1_op = 0x08,
134 sdxc1_op = 0x09, madd_s_op = 0x20,
135 madd_d_op = 0x21, madd_e_op = 0x22,
136 msub_s_op = 0x28, msub_d_op = 0x29,
137 msub_e_op = 0x2a, nmadd_s_op = 0x30,
138 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
139 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
140 nmsub_e_op = 0x3a
141 };
142
143 /*
144 * func field for mad opcodes (MIPS IV).
145 */
146 enum mad_func {
147 madd_op = 0x08, msub_op = 0x0a,
148 nmadd_op = 0x0c, nmsub_op = 0x0e
149 };
150
151 /*
152 * Damn ... bitfields depend from byteorder :-(
153 */
154 #ifdef __MIPSEB__
155 struct j_format { /* Jump format */
156 unsigned int opcode : 6;
157 unsigned int target : 26;
158 };
159
160 struct i_format { /* Immediate format (addi, lw, ...) */
161 unsigned int opcode : 6;
162 unsigned int rs : 5;
163 unsigned int rt : 5;
164 signed int simmediate : 16;
165 };
166
167 struct u_format { /* Unsigned immediate format (ori, xori, ...) */
168 unsigned int opcode : 6;
169 unsigned int rs : 5;
170 unsigned int rt : 5;
171 unsigned int uimmediate : 16;
172 };
173
174 struct c_format { /* Cache (>= R6000) format */
175 unsigned int opcode : 6;
176 unsigned int rs : 5;
177 unsigned int c_op : 3;
178 unsigned int cache : 2;
179 unsigned int simmediate : 16;
180 };
181
182 struct r_format { /* Register format */
183 unsigned int opcode : 6;
184 unsigned int rs : 5;
185 unsigned int rt : 5;
186 unsigned int rd : 5;
187 unsigned int re : 5;
188 unsigned int func : 6;
189 };
190
191 struct p_format { /* Performance counter format (R10000) */
192 unsigned int opcode : 6;
193 unsigned int rs : 5;
194 unsigned int rt : 5;
195 unsigned int rd : 5;
196 unsigned int re : 5;
197 unsigned int func : 6;
198 };
199
200 struct f_format { /* FPU register format */
201 unsigned int opcode : 6;
202 unsigned int : 1;
203 unsigned int fmt : 4;
204 unsigned int rt : 5;
205 unsigned int rd : 5;
206 unsigned int re : 5;
207 unsigned int func : 6;
208 };
209
210 struct ma_format { /* FPU multipy and add format (MIPS IV) */
211 unsigned int opcode : 6;
212 unsigned int fr : 5;
213 unsigned int ft : 5;
214 unsigned int fs : 5;
215 unsigned int fd : 5;
216 unsigned int func : 4;
217 unsigned int fmt : 2;
218 };
219
220 #elif defined(__MIPSEL__)
221
222 struct j_format { /* Jump format */
223 unsigned int target : 26;
224 unsigned int opcode : 6;
225 };
226
227 struct i_format { /* Immediate format */
228 signed int simmediate : 16;
229 unsigned int rt : 5;
230 unsigned int rs : 5;
231 unsigned int opcode : 6;
232 };
233
234 struct u_format { /* Unsigned immediate format */
235 unsigned int uimmediate : 16;
236 unsigned int rt : 5;
237 unsigned int rs : 5;
238 unsigned int opcode : 6;
239 };
240
241 struct c_format { /* Cache (>= R6000) format */
242 unsigned int simmediate : 16;
243 unsigned int cache : 2;
244 unsigned int c_op : 3;
245 unsigned int rs : 5;
246 unsigned int opcode : 6;
247 };
248
249 struct r_format { /* Register format */
250 unsigned int func : 6;
251 unsigned int re : 5;
252 unsigned int rd : 5;
253 unsigned int rt : 5;
254 unsigned int rs : 5;
255 unsigned int opcode : 6;
256 };
257
258 struct p_format { /* Performance counter format (R10000) */
259 unsigned int func : 6;
260 unsigned int re : 5;
261 unsigned int rd : 5;
262 unsigned int rt : 5;
263 unsigned int rs : 5;
264 unsigned int opcode : 6;
265 };
266
267 struct f_format { /* FPU register format */
268 unsigned int func : 6;
269 unsigned int re : 5;
270 unsigned int rd : 5;
271 unsigned int rt : 5;
272 unsigned int fmt : 4;
273 unsigned int : 1;
274 unsigned int opcode : 6;
275 };
276
277 struct ma_format { /* FPU multipy and add format (MIPS IV) */
278 unsigned int fmt : 2;
279 unsigned int func : 4;
280 unsigned int fd : 5;
281 unsigned int fs : 5;
282 unsigned int ft : 5;
283 unsigned int fr : 5;
284 unsigned int opcode : 6;
285 };
286
287 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
288 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
289 #endif
290
291 union mips_instruction {
292 unsigned int word;
293 unsigned short halfword[2];
294 unsigned char byte[4];
295 struct j_format j_format;
296 struct i_format i_format;
297 struct u_format u_format;
298 struct c_format c_format;
299 struct r_format r_format;
300 struct f_format f_format;
301 struct ma_format ma_format;
302 };
303
304 #endif /* __ASM_MIPS_INST_H */
305
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