1 /* $Id: io.h,v 1.13 2000/02/24 00:13:19 ralf Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1994, 1995 Waldorf GmbH
8 * Copyright (C) 1994 - 2000 Ralf Baechle
9 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 */
11 #ifndef _ASM_IO_H
12 #define _ASM_IO_H
13
14 /*
15 * Slowdown I/O port space accesses for antique hardware.
16 */
17 #undef CONF_SLOWDOWN_IO
18
19 #include <asm/addrspace.h>
20
21 /*
22 * This file contains the definitions for the MIPS counterpart of the
23 * x86 in/out instructions. This heap of macros and C results in much
24 * better code than the approach of doing it in plain C. The macros
25 * result in code that is to fast for certain hardware. On the other
26 * side the performance of the string functions should be improved for
27 * sake of certain devices like EIDE disks that do highspeed polled I/O.
28 *
29 * Ralf
30 *
31 * This file contains the definitions for the x86 IO instructions
32 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
33 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
34 * versions of the single-IO instructions (inb_p/inw_p/..).
35 *
36 * This file is not meant to be obfuscating: it's just complicated
37 * to (a) handle it all in a way that makes gcc able to optimize it
38 * as well as possible and (b) trying to avoid writing the same thing
39 * over and over again with slight variations and possibly making a
40 * mistake somewhere.
41 */
42
43 /*
44 * On MIPS I/O ports are memory mapped, so we access them using normal
45 * load/store instructions. mips_io_port_base is the virtual address to
46 * which all ports are being mapped. For sake of efficiency some code
47 * assumes that this is an address that can be loaded with a single lui
48 * instruction, so the lower 16 bits must be zero. Should be true on
49 * on any sane architecture; generic code does not use this assumption.
50 */
51 extern unsigned long mips_io_port_base;
52
53 /*
54 * Thanks to James van Artsdalen for a better timing-fix than
55 * the two short jumps: using outb's to a nonexistent port seems
56 * to guarantee better timings even on fast machines.
57 *
58 * On the other hand, I'd like to be sure of a non-existent port:
59 * I feel a bit unsafe about using 0x80 (should be safe, though)
60 *
61 * Linus
62 *
63 */
64
65 #define __SLOW_DOWN_IO \
66 __asm__ __volatile__( \
67 "sb\t$0,0x80(%0)" \
68 : : "r" (mips_io_port_base));
69
70 #ifdef CONF_SLOWDOWN_IO
71 #ifdef REALLY_SLOW_IO
72 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
73 #else
74 #define SLOW_DOWN_IO __SLOW_DOWN_IO
75 #endif
76 #else
77 #define SLOW_DOWN_IO
78 #endif
79
80 /*
81 * Change virtual addresses to physical addresses and vv.
82 * These are trivial on the 1:1 Linux/MIPS mapping
83 */
84 extern inline unsigned long virt_to_phys(volatile void * address)
85 {
86 return PHYSADDR(address);
87 }
88
89 extern inline void * phys_to_virt(unsigned long address)
90 {
91 return (void *)KSEG0ADDR(address);
92 }
93
94 extern void * ioremap(unsigned long phys_addr, unsigned long size);
95 extern void iounmap(void *addr);
96
97 /*
98 * IO bus memory addresses are also 1:1 with the physical address
99 */
100 extern inline unsigned long virt_to_bus(volatile void * address)
101 {
102 return PHYSADDR(address);
103 }
104
105 extern inline void * bus_to_virt(unsigned long address)
106 {
107 return (void *)KSEG0ADDR(address);
108 }
109
110 /*
111 * isa_slot_offset is the address where E(ISA) busaddress 0 is is mapped
112 * for the processor.
113 */
114 extern unsigned long isa_slot_offset;
115
116 /*
117 * readX/writeX() are used to access memory mapped devices. On some
118 * architectures the memory mapped IO stuff needs to be accessed
119 * differently. On the x86 architecture, we just read/write the
120 * memory location directly.
121 *
122 * On MIPS, we have the whole physical address space mapped at all
123 * times, so "ioremap()" and "iounmap()" do not need to do anything.
124 * (This isn't true for all machines but we still handle these cases
125 * with wired TLB entries anyway ...)
126 *
127 * We cheat a bit and always return uncachable areas until we've fixed
128 * the drivers to handle caching properly.
129 */
130 extern inline void * ioremap(unsigned long offset, unsigned long size)
131 {
132 return (void *) KSEG1ADDR(offset);
133 }
134
135 /*
136 * This one maps high address device memory and turns off caching for that area.
137 * it's useful if some control registers are in such an area and write combining
138 * or read caching is not desirable:
139 */
140 extern inline void * ioremap_nocache (unsigned long offset, unsigned long size)
141 {
142 return (void *) KSEG1ADDR(offset);
143 }
144
145 extern inline void iounmap(void *addr)
146 {
147 }
148
149 /*
150 * XXX We need system specific versions of these to handle EISA address bits
151 * 24-31 on SNI.
152 * XXX more SNI hacks.
153 */
154 #define readb(addr) (*(volatile unsigned char *)(addr))
155 #define readw(addr) (*(volatile unsigned short *)(addr))
156 #define readl(addr) (*(volatile unsigned int *)(addr))
157 #define __raw_readb readb
158 #define __raw_readw readw
159 #define __raw_readl readl
160
161 #define writeb(b,addr) (*(volatile unsigned char *)(addr)) = (b)
162 #define writew(b,addr) (*(volatile unsigned short *)(addr)) = (b)
163 #define writel(b,addr) (*(volatile unsigned int *)(addr)) = (b)
164 #define __raw_writeb writeb
165 #define __raw_writew writew
166 #define __raw_writel writel
167
168 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
169 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
170 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
171
172 /* END SNI HACKS ... */
173
174 /*
175 * ISA space is 'always mapped' on currently supported MIPS systems, no need
176 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
177 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
178 * are physical addresses. The following constant pointer can be
179 * used as the IO-area pointer (it can be iounmapped as well, so the
180 * analogy with PCI is quite large):
181 */
182 #define __ISA_IO_base ((char *)(PAGE_OFFSET))
183
184 #define isa_readb(a) readb(a)
185 #define isa_readw(a) readw(a)
186 #define isa_readl(a) readl(a)
187 #define isa_writeb(b,a) writeb(b,a)
188 #define isa_writew(w,a) writew(w,a)
189 #define isa_writel(l,a) writel(l,a)
190
191 #define isa_memset_io(a,b,c) memset_io((a),(b),(c))
192 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),(b),(c))
193 #define isa_memcpy_toio(a,b,c) memcpy_toio((a),(b),(c))
194
195 /*
196 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
197 * just copy it. The net code will then do the checksum later.
198 */
199 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
200 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
201
202 static inline int check_signature(unsigned long io_addr,
203 const unsigned char *signature, int length)
204 {
205 int retval = 0;
206 do {
207 if (readb(io_addr) != *signature)
208 goto out;
209 io_addr++;
210 signature++;
211 length--;
212 } while (length);
213 retval = 1;
214 out:
215 return retval;
216 }
217 #define isa_check_signature(io, s, l) check_signature(i,s,l)
218
219 /*
220 * Talk about misusing macros..
221 */
222
223 #define __OUT1(s) \
224 extern inline void __out##s(unsigned int value, unsigned int port) {
225
226 #define __OUT2(m) \
227 __asm__ __volatile__ ("s" #m "\t%0,%1(%2)"
228
229 #define __OUT(m,s) \
230 __OUT1(s) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); } \
231 __OUT1(s##c) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); } \
232 __OUT1(s##_p) __OUT2(m) : : "r" (value), "i" (0), "r" (mips_io_port_base+port)); \
233 SLOW_DOWN_IO; } \
234 __OUT1(s##c_p) __OUT2(m) : : "r" (value), "ir" (port), "r" (mips_io_port_base)); \
235 SLOW_DOWN_IO; }
236
237 #define __IN1(t,s) \
238 extern __inline__ t __in##s(unsigned int port) { t _v;
239
240 /*
241 * Required nops will be inserted by the assembler
242 */
243 #define __IN2(m) \
244 __asm__ __volatile__ ("l" #m "\t%0,%1(%2)"
245
246 #define __IN(t,m,s) \
247 __IN1(t,s) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); return _v; } \
248 __IN1(t,s##c) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); return _v; } \
249 __IN1(t,s##_p) __IN2(m) : "=r" (_v) : "i" (0), "r" (mips_io_port_base+port)); SLOW_DOWN_IO; return _v; } \
250 __IN1(t,s##c_p) __IN2(m) : "=r" (_v) : "ir" (port), "r" (mips_io_port_base)); SLOW_DOWN_IO; return _v; }
251
252 #define __INS1(s) \
253 extern inline void __ins##s(unsigned int port, void * addr, unsigned long count) {
254
255 #define __INS2(m) \
256 if (count) \
257 __asm__ __volatile__ ( \
258 ".set\tnoreorder\n\t" \
259 ".set\tnoat\n" \
260 "1:\tl" #m "\t$1,%4(%5)\n\t" \
261 "subu\t%1,1\n\t" \
262 "s" #m "\t$1,(%0)\n\t" \
263 "bne\t$0,%1,1b\n\t" \
264 "addiu\t%0,%6\n\t" \
265 ".set\tat\n\t" \
266 ".set\treorder"
267
268 #define __INS(m,s,i) \
269 __INS1(s) __INS2(m) \
270 : "=r" (addr), "=r" (count) \
271 : "" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
272 : "$1");} \
273 __INS1(s##c) __INS2(m) \
274 : "=r" (addr), "=r" (count) \
275 : "" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
276 : "$1");}
277
278 #define __OUTS1(s) \
279 extern inline void __outs##s(unsigned int port, const void * addr, unsigned long count) {
280
281 #define __OUTS2(m) \
282 if (count) \
283 __asm__ __volatile__ ( \
284 ".set\tnoreorder\n\t" \
285 ".set\tnoat\n" \
286 "1:\tl" #m "\t$1,(%0)\n\t" \
287 "subu\t%1,1\n\t" \
288 "s" #m "\t$1,%4(%5)\n\t" \
289 "bne\t$0,%1,1b\n\t" \
290 "addiu\t%0,%6\n\t" \
291 ".set\tat\n\t" \
292 ".set\treorder"
293
294 #define __OUTS(m,s,i) \
295 __OUTS1(s) __OUTS2(m) \
296 : "=r" (addr), "=r" (count) \
297 : "" (addr), "1" (count), "i" (0), "r" (mips_io_port_base+port), "I" (i) \
298 : "$1");} \
299 __OUTS1(s##c) __OUTS2(m) \
300 : "=r" (addr), "=r" (count) \
301 : "" (addr), "1" (count), "ir" (port), "r" (mips_io_port_base), "I" (i) \
302 : "$1");}
303
304 __IN(unsigned char,b,b)
305 __IN(unsigned short,h,w)
306 __IN(unsigned int,w,l)
307
308 __OUT(b,b)
309 __OUT(h,w)
310 __OUT(w,l)
311
312 __INS(b,b,1)
313 __INS(h,w,2)
314 __INS(w,l,4)
315
316 __OUTS(b,b,1)
317 __OUTS(h,w,2)
318 __OUTS(w,l,4)
319
320 /*
321 * Note that due to the way __builtin_constant_p() works, you
322 * - can't use it inside an inline function (it will never be true)
323 * - you don't have to worry about side effects within the __builtin..
324 */
325 #define outb(val,port) \
326 ((__builtin_constant_p((port)) && (port) < 32768) ? \
327 __outbc((val),(port)) : \
328 __outb((val),(port)))
329
330 #define inb(port) \
331 ((__builtin_constant_p((port)) && (port) < 32768) ? \
332 __inbc(port) : \
333 __inb(port))
334
335 #define outb_p(val,port) \
336 ((__builtin_constant_p((port)) && (port) < 32768) ? \
337 __outbc_p((val),(port)) : \
338 __outb_p((val),(port)))
339
340 #define inb_p(port) \
341 ((__builtin_constant_p((port)) && (port) < 32768) ? \
342 __inbc_p(port) : \
343 __inb_p(port))
344
345 #define outw(val,port) \
346 ((__builtin_constant_p((port)) && (port) < 32768) ? \
347 __outwc((val),(port)) : \
348 __outw((val),(port)))
349
350 #define inw(port) \
351 ((__builtin_constant_p((port)) && (port) < 32768) ? \
352 __inwc(port) : \
353 __inw(port))
354
355 #define outw_p(val,port) \
356 ((__builtin_constant_p((port)) && (port) < 32768) ? \
357 __outwc_p((val),(port)) : \
358 __outw_p((val),(port)))
359
360 #define inw_p(port) \
361 ((__builtin_constant_p((port)) && (port) < 32768) ? \
362 __inwc_p(port) : \
363 __inw_p(port))
364
365 #define outl(val,port) \
366 ((__builtin_constant_p((port)) && (port) < 32768) ? \
367 __outlc((val),(port)) : \
368 __outl((val),(port)))
369
370 #define inl(port) \
371 ((__builtin_constant_p((port)) && (port) < 32768) ? \
372 __inlc(port) : \
373 __inl(port))
374
375 #define outl_p(val,port) \
376 ((__builtin_constant_p((port)) && (port) < 32768) ? \
377 __outlc_p((val),(port)) : \
378 __outl_p((val),(port)))
379
380 #define inl_p(port) \
381 ((__builtin_constant_p((port)) && (port) < 32768) ? \
382 __inlc_p(port) : \
383 __inl_p(port))
384
385
386 #define outsb(port,addr,count) \
387 ((__builtin_constant_p((port)) && (port) < 32768) ? \
388 __outsbc((port),(addr),(count)) : \
389 __outsb ((port),(addr),(count)))
390
391 #define insb(port,addr,count) \
392 ((__builtin_constant_p((port)) && (port) < 32768) ? \
393 __insbc((port),(addr),(count)) : \
394 __insb((port),(addr),(count)))
395
396 #define outsw(port,addr,count) \
397 ((__builtin_constant_p((port)) && (port) < 32768) ? \
398 __outswc((port),(addr),(count)) : \
399 __outsw ((port),(addr),(count)))
400
401 #define insw(port,addr,count) \
402 ((__builtin_constant_p((port)) && (port) < 32768) ? \
403 __inswc((port),(addr),(count)) : \
404 __insw((port),(addr),(count)))
405
406 #define outsl(port,addr,count) \
407 ((__builtin_constant_p((port)) && (port) < 32768) ? \
408 __outslc((port),(addr),(count)) : \
409 __outsl ((port),(addr),(count)))
410
411 #define insl(port,addr,count) \
412 ((__builtin_constant_p((port)) && (port) < 32768) ? \
413 __inslc((port),(addr),(count)) : \
414 __insl((port),(addr),(count)))
415
416 #define IO_SPACE_LIMIT 0xffff
417
418 /*
419 * The caches on some architectures aren't dma-coherent and have need to
420 * handle this in software. There are three types of operations that
421 * can be applied to dma buffers.
422 *
423 * - dma_cache_wback_inv(start, size) makes caches and coherent by
424 * writing the content of the caches back to memory, if necessary.
425 * The function also invalidates the affected part of the caches as
426 * necessary before DMA transfers from outside to memory.
427 * - dma_cache_wback(start, size) makes caches and coherent by
428 * writing the content of the caches back to memory, if necessary.
429 * The function also invalidates the affected part of the caches as
430 * necessary before DMA transfers from outside to memory.
431 * - dma_cache_inv(start, size) invalidates the affected parts of the
432 * caches. Dirty lines of the caches may be written back or simply
433 * be discarded. This operation is necessary before dma operations
434 * to the memory.
435 */
436 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
437 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
438 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
439
440 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
441 #define dma_cache_wback(start,size) _dma_cache_wback(start,size)
442 #define dma_cache_inv(start,size) _dma_cache_inv(start,size)
443
444 #endif /* _ASM_IO_H */
445
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