1 /* $Id: mipsregs.h,v 1.6 1999/07/26 19:42:43 harald Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1994, 1995, 1996, 1997 by Ralf Baechle
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 */
10 #ifndef __ASM_MIPS_MIPSREGS_H
11 #define __ASM_MIPS_MIPSREGS_H
12
13 #include <linux/linkage.h>
14
15 /*
16 * The following macros are especially useful for __asm__
17 * inline assembler.
18 */
19 #ifndef __STR
20 #define __STR(x) #x
21 #endif
22 #ifndef STR
23 #define STR(x) __STR(x)
24 #endif
25
26 /*
27 * Coprocessor 0 register names
28 */
29 #define CP0_INDEX $0
30 #define CP0_RANDOM $1
31 #define CP0_ENTRYLO0 $2
32 #define CP0_ENTRYLO1 $3
33 #define CP0_CONF $3
34 #define CP0_CONTEXT $4
35 #define CP0_PAGEMASK $5
36 #define CP0_WIRED $6
37 #define CP0_BADVADDR $8
38 #define CP0_COUNT $9
39 #define CP0_ENTRYHI $10
40 #define CP0_COMPARE $11
41 #define CP0_STATUS $12
42 #define CP0_CAUSE $13
43 #define CP0_EPC $14
44 #define CP0_PRID $15
45 #define CP0_CONFIG $16
46 #define CP0_LLADDR $17
47 #define CP0_WATCHLO $18
48 #define CP0_WATCHHI $19
49 #define CP0_XCONTEXT $20
50 #define CP0_FRAMEMASK $21
51 #define CP0_DIAGNOSTIC $22
52 #define CP0_PERFORMANCE $25
53 #define CP0_ECC $26
54 #define CP0_CACHEERR $27
55 #define CP0_TAGLO $28
56 #define CP0_TAGHI $29
57 #define CP0_ERROREPC $30
58
59 /*
60 * R4640/R4650 cp0 register names. These registers are listed
61 * here only for completeness; without MMU these CPUs are not useable
62 * by Linux. A future ELKS port might take make Linux run on them
63 * though ...
64 */
65 #define CP0_IBASE $0
66 #define CP0_IBOUND $1
67 #define CP0_DBASE $2
68 #define CP0_DBOUND $3
69 #define CP0_CALG $17
70 #define CP0_IWATCH $18
71 #define CP0_DWATCH $19
72
73 /*
74 * Coprocessor 1 (FPU) register names
75 */
76 #define CP1_REVISION $0
77 #define CP1_STATUS $31
78
79 /*
80 * Values for PageMask register
81 */
82 #define PM_4K 0x00000000
83 #define PM_16K 0x00006000
84 #define PM_64K 0x0001e000
85 #define PM_256K 0x0007e000
86 #define PM_1M 0x001fe000
87 #define PM_4M 0x007fe000
88 #define PM_16M 0x01ffe000
89
90 /*
91 * Values used for computation of new tlb entries
92 */
93 #define PL_4K 12
94 #define PL_16K 14
95 #define PL_64K 16
96 #define PL_256K 18
97 #define PL_1M 20
98 #define PL_4M 22
99 #define PL_16M 24
100
101 /*
102 * Macros to access the system control coprocessor
103 */
104 #define read_32bit_cp0_register(source) \
105 ({ int __res; \
106 __asm__ __volatile__( \
107 ".set\tpush\n\t" \
108 ".set\treorder\n\t" \
109 "mfc0\t%0,"STR(source)"\n\t" \
110 ".set\tpop" \
111 : "=r" (__res)); \
112 __res;})
113
114 /*
115 * For now use this only with interrupts disabled!
116 */
117 #define read_64bit_cp0_register(source) \
118 ({ int __res; \
119 __asm__ __volatile__( \
120 ".set\tmips3\n\t" \
121 "dmfc0\t%0,"STR(source)"\n\t" \
122 ".set\tmips0" \
123 : "=r" (__res)); \
124 __res;})
125
126 #define write_32bit_cp0_register(register,value) \
127 __asm__ __volatile__( \
128 "mtc0\t%0,"STR(register)"\n\t" \
129 "nop" \
130 : : "r" (value));
131
132 #define write_64bit_cp0_register(register,value) \
133 __asm__ __volatile__( \
134 ".set\tmips3\n\t" \
135 "dmtc0\t%0,"STR(register)"\n\t" \
136 ".set\tmips0" \
137 : : "r" (value))
138 /*
139 * R4x00 interrupt enable / cause bits
140 */
141 #define IE_SW0 (1<< 8)
142 #define IE_SW1 (1<< 9)
143 #define IE_IRQ0 (1<<10)
144 #define IE_IRQ1 (1<<11)
145 #define IE_IRQ2 (1<<12)
146 #define IE_IRQ3 (1<<13)
147 #define IE_IRQ4 (1<<14)
148 #define IE_IRQ5 (1<<15)
149
150 /*
151 * R4x00 interrupt cause bits
152 */
153 #define C_SW0 (1<< 8)
154 #define C_SW1 (1<< 9)
155 #define C_IRQ0 (1<<10)
156 #define C_IRQ1 (1<<11)
157 #define C_IRQ2 (1<<12)
158 #define C_IRQ3 (1<<13)
159 #define C_IRQ4 (1<<14)
160 #define C_IRQ5 (1<<15)
161
162 #ifndef _LANGUAGE_ASSEMBLY
163 /*
164 * Manipulate the status register.
165 * Mostly used to access the interrupt bits.
166 */
167 #define __BUILD_SET_CP0(name,register) \
168 extern __inline__ unsigned int \
169 set_cp0_##name(unsigned int change, unsigned int new) \
170 { \
171 unsigned int res; \
172 \
173 res = read_32bit_cp0_register(register); \
174 res &= ~change; \
175 res |= (new & change); \
176 if(change) \
177 write_32bit_cp0_register(register, res); \
178 \
179 return res; \
180 }
181
182 __BUILD_SET_CP0(status,CP0_STATUS)
183 __BUILD_SET_CP0(cause,CP0_CAUSE)
184 __BUILD_SET_CP0(config,CP0_CONFIG)
185
186 #endif /* defined (_LANGUAGE_ASSEMBLY) */
187
188 /*
189 * Inline code for use of the ll and sc instructions
190 *
191 * FIXME: This instruction is only available on MIPS ISA >=2.
192 * Since these operations are only being used for atomic operations
193 * the easiest workaround for the R[23]00 is to disable interrupts.
194 * This fails for R3000 SMP machines which use that many different
195 * technologies as replacement that it is difficult to create even
196 * just a hook for for all machines to hook into. The only good
197 * thing is that there is currently no R3000 SMP machine on the
198 * Linux/MIPS target list ...
199 */
200 #define load_linked(addr) \
201 ({ \
202 unsigned int __res; \
203 \
204 __asm__ __volatile__( \
205 "ll\t%0,(%1)" \
206 : "=r" (__res) \
207 : "r" ((unsigned long) (addr))); \
208 \
209 __res; \
210 })
211
212 #define store_conditional(addr,value) \
213 ({ \
214 int __res; \
215 \
216 __asm__ __volatile__( \
217 "sc\t%0,(%2)" \
218 : "=r" (__res) \
219 : "" (value), "r" (addr)); \
220 \
221 __res; \
222 })
223
224 /*
225 * Bitfields in the R4xx0 cp0 status register
226 */
227 #define ST0_IE 0x00000001
228 #define ST0_EXL 0x00000002
229 #define ST0_ERL 0x00000004
230 #define ST0_KSU 0x00000018
231 # define KSU_USER 0x00000010
232 # define KSU_SUPERVISOR 0x00000008
233 # define KSU_KERNEL 0x00000000
234 #define ST0_UX 0x00000020
235 #define ST0_SX 0x00000040
236 #define ST0_KX 0x00000080
237 #define ST0_DE 0x00010000
238 #define ST0_CE 0x00020000
239
240 /*
241 * Bitfields in the R[23]000 cp0 status register.
242 */
243 #define ST0_IEC 0x00000001
244 #define ST0_KUC 0x00000002
245 #define ST0_IEP 0x00000004
246 #define ST0_KUP 0x00000008
247 #define ST0_IEO 0x00000010
248 #define ST0_KUO 0x00000020
249 /* bits 6 & 7 are reserved on R[23]000 */
250 #define ST0_ISC 0x00010000
251 #define ST0_SWC 0x00020000
252
253 /*
254 * Bits specific to the R4640/R4650
255 */
256 #define ST0_UM <1 << 4)
257 #define ST0_IL (1 << 23)
258 #define ST0_DL (1 << 24)
259
260 /*
261 * Status register bits available in all MIPS CPUs.
262 */
263 #define ST0_IM 0x0000ff00
264 #define STATUSB_IP0 8
265 #define STATUSF_IP0 (1 << 8)
266 #define STATUSB_IP1 9
267 #define STATUSF_IP1 (1 << 9)
268 #define STATUSB_IP2 10
269 #define STATUSF_IP2 (1 << 10)
270 #define STATUSB_IP3 11
271 #define STATUSF_IP3 (1 << 11)
272 #define STATUSB_IP4 12
273 #define STATUSF_IP4 (1 << 12)
274 #define STATUSB_IP5 13
275 #define STATUSF_IP5 (1 << 13)
276 #define STATUSB_IP6 14
277 #define STATUSF_IP6 (1 << 14)
278 #define STATUSB_IP7 15
279 #define STATUSF_IP7 (1 << 15)
280 #define ST0_CH 0x00040000
281 #define ST0_SR 0x00100000
282 #define ST0_BEV 0x00400000
283 #define ST0_RE 0x02000000
284 #define ST0_FR 0x04000000
285 #define ST0_CU 0xf0000000
286 #define ST0_CU0 0x10000000
287 #define ST0_CU1 0x20000000
288 #define ST0_CU2 0x40000000
289 #define ST0_CU3 0x80000000
290 #define ST0_XX 0x80000000 /* MIPS IV naming */
291
292 /*
293 * Bitfields and bit numbers in the coprocessor 0 cause register.
294 *
295 * Refer to to your MIPS R4xx0 manual, chapter 5 for explanation.
296 */
297 #define CAUSEB_EXCCODE 2
298 #define CAUSEF_EXCCODE (31 << 2)
299 #define CAUSEB_IP 8
300 #define CAUSEF_IP (255 << 8)
301 #define CAUSEB_IP0 8
302 #define CAUSEF_IP0 (1 << 8)
303 #define CAUSEB_IP1 9
304 #define CAUSEF_IP1 (1 << 9)
305 #define CAUSEB_IP2 10
306 #define CAUSEF_IP2 (1 << 10)
307 #define CAUSEB_IP3 11
308 #define CAUSEF_IP3 (1 << 11)
309 #define CAUSEB_IP4 12
310 #define CAUSEF_IP4 (1 << 12)
311 #define CAUSEB_IP5 13
312 #define CAUSEF_IP5 (1 << 13)
313 #define CAUSEB_IP6 14
314 #define CAUSEF_IP6 (1 << 14)
315 #define CAUSEB_IP7 15
316 #define CAUSEF_IP7 (1 << 15)
317 #define CAUSEB_IV 23
318 #define CAUSEF_IV (1 << 23)
319 #define CAUSEB_CE 28
320 #define CAUSEF_CE (3 << 28)
321 #define CAUSEB_BD 31
322 #define CAUSEF_BD (1 << 31)
323
324 /*
325 * Bits in the coprozessor 0 config register.
326 */
327 #define CONF_CM_CACHABLE_NO_WA 0
328 #define CONF_CM_CACHABLE_WA 1
329 #define CONF_CM_UNCACHED 2
330 #define CONF_CM_CACHABLE_NONCOHERENT 3
331 #define CONF_CM_CACHABLE_CE 4
332 #define CONF_CM_CACHABLE_COW 5
333 #define CONF_CM_CACHABLE_CUW 6
334 #define CONF_CM_CACHABLE_ACCELERATED 7
335 #define CONF_CM_CMASK 7
336 #define CONF_DB (1 << 4)
337 #define CONF_IB (1 << 5)
338 #define CONF_SC (1 << 17)
339 #define CONF_AC (1 << 23)
340 #define CONF_HALT (1 << 25)
341
342 /*
343 * R10000 performance counter definitions.
344 *
345 * FIXME: The R10000 performance counter opens a nice way to implement CPU
346 * time accounting with a precission of one cycle. I don't have
347 * R10000 silicon but just a manual, so ...
348 */
349
350 /*
351 * Events counted by counter #0
352 */
353 #define CE0_CYCLES 0
354 #define CE0_INSN_ISSUED 1
355 #define CE0_LPSC_ISSUED 2
356 #define CE0_S_ISSUED 3
357 #define CE0_SC_ISSUED 4
358 #define CE0_SC_FAILED 5
359 #define CE0_BRANCH_DECODED 6
360 #define CE0_QW_WB_SECONDARY 7
361 #define CE0_CORRECTED_ECC_ERRORS 8
362 #define CE0_ICACHE_MISSES 9
363 #define CE0_SCACHE_I_MISSES 10
364 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
365 #define CE0_EXT_INTERVENTIONS_REQ 12
366 #define CE0_EXT_INVALIDATE_REQ 13
367 #define CE0_VIRTUAL_COHERENCY_COND 14
368 #define CE0_INSN_GRADUATED 15
369
370 /*
371 * Events counted by counter #1
372 */
373 #define CE1_CYCLES 0
374 #define CE1_INSN_GRADUATED 1
375 #define CE1_LPSC_GRADUATED 2
376 #define CE1_S_GRADUATED 3
377 #define CE1_SC_GRADUATED 4
378 #define CE1_FP_INSN_GRADUATED 5
379 #define CE1_QW_WB_PRIMARY 6
380 #define CE1_TLB_REFILL 7
381 #define CE1_BRANCH_MISSPREDICTED 8
382 #define CE1_DCACHE_MISS 9
383 #define CE1_SCACHE_D_MISSES 10
384 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
385 #define CE1_EXT_INTERVENTION_HITS 12
386 #define CE1_EXT_INVALIDATE_REQ 13
387 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
388 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
389
390 /*
391 * These flags define in which priviledge mode the counters count events
392 */
393 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
394 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
395 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
396 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
397
398 #ifndef _LANGUAGE_ASSEMBLY
399 /*
400 * Functions to access the performance counter and control registers
401 */
402 extern asmlinkage unsigned int read_perf_cntr(unsigned int counter);
403 extern asmlinkage void write_perf_cntr(unsigned int counter, unsigned int val);
404 extern asmlinkage unsigned int read_perf_cntl(unsigned int counter);
405 extern asmlinkage void write_perf_cntl(unsigned int counter, unsigned int val);
406 #endif
407
408 #endif /* __ASM_MIPS_MIPSREGS_H */
409
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