1 /*
2 * include/asm-mips/stackframe.h
3 *
4 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle and Paul M. Antoine.
5 *
6 * $Id: stackframe.h,v 1.10 1999/08/13 17:07:27 harald Exp $
7 */
8 #ifndef __ASM_MIPS_STACKFRAME_H
9 #define __ASM_MIPS_STACKFRAME_H
10
11 #include <asm/asm.h>
12 #include <asm/offset.h>
13 #include <linux/config.h>
14
15 #define SAVE_AT \
16 .set push; \
17 .set noat; \
18 sw $1, PT_R1(sp); \
19 .set pop
20
21 #define SAVE_TEMP \
22 mfhi v1; \
23 sw $8, PT_R8(sp); \
24 sw $9, PT_R9(sp); \
25 sw v1, PT_HI(sp); \
26 mflo v1; \
27 sw $10,PT_R10(sp); \
28 sw $11, PT_R11(sp); \
29 sw v1, PT_LO(sp); \
30 sw $12, PT_R12(sp); \
31 sw $13, PT_R13(sp); \
32 sw $14, PT_R14(sp); \
33 sw $15, PT_R15(sp); \
34 sw $24, PT_R24(sp)
35
36 #define SAVE_STATIC \
37 sw $16, PT_R16(sp); \
38 sw $17, PT_R17(sp); \
39 sw $18, PT_R18(sp); \
40 sw $19, PT_R19(sp); \
41 sw $20, PT_R20(sp); \
42 sw $21, PT_R21(sp); \
43 sw $22, PT_R22(sp); \
44 sw $23, PT_R23(sp); \
45 sw $30, PT_R30(sp)
46
47 #define __str2(x) #x
48 #define __str(x) __str2(x)
49
50 #define save_static(frame) \
51 __asm__ __volatile__( \
52 "sw\t$16,"__str(PT_R16)"(%0)\n\t" \
53 "sw\t$17,"__str(PT_R17)"(%0)\n\t" \
54 "sw\t$18,"__str(PT_R18)"(%0)\n\t" \
55 "sw\t$19,"__str(PT_R19)"(%0)\n\t" \
56 "sw\t$20,"__str(PT_R20)"(%0)\n\t" \
57 "sw\t$21,"__str(PT_R21)"(%0)\n\t" \
58 "sw\t$22,"__str(PT_R22)"(%0)\n\t" \
59 "sw\t$23,"__str(PT_R23)"(%0)\n\t" \
60 "sw\t$30,"__str(PT_R30)"(%0)\n\t" \
61 : /* No outputs */ \
62 : "r" (frame))
63
64 #define SAVE_SOME \
65 .set push; \
66 .set reorder; \
67 mfc0 k0, CP0_STATUS; \
68 sll k0, 3; /* extract cu0 bit */ \
69 .set noreorder; \
70 bltz k0, 8f; \
71 move k1, sp; \
72 .set reorder; \
73 /* Called from user mode, new stack. */ \
74 lui k1, %hi(kernelsp); \
75 lw k1, %lo(kernelsp)(k1); \
76 8: \
77 move k0, sp; \
78 subu sp, k1, PT_SIZE; \
79 sw k0, PT_R29(sp); \
80 sw $3, PT_R3(sp); \
81 sw $0, PT_R0(sp); \
82 mfc0 v1, CP0_STATUS; \
83 sw $2, PT_R2(sp); \
84 sw v1, PT_STATUS(sp); \
85 sw $4, PT_R4(sp); \
86 mfc0 v1, CP0_CAUSE; \
87 sw $5, PT_R5(sp); \
88 sw v1, PT_CAUSE(sp); \
89 sw $6, PT_R6(sp); \
90 mfc0 v1, CP0_EPC; \
91 sw $7, PT_R7(sp); \
92 sw v1, PT_EPC(sp); \
93 sw $25, PT_R25(sp); \
94 sw $28, PT_R28(sp); \
95 sw $31, PT_R31(sp); \
96 ori $28, sp, 0x1fff; \
97 xori $28, 0x1fff; \
98 .set pop
99
100 #define SAVE_ALL \
101 SAVE_SOME; \
102 SAVE_AT; \
103 SAVE_TEMP; \
104 SAVE_STATIC
105
106 #define RESTORE_AT \
107 .set push; \
108 .set noat; \
109 lw $1, PT_R1(sp); \
110 .set pop;
111
112 #define RESTORE_TEMP \
113 lw $24, PT_LO(sp); \
114 lw $8, PT_R8(sp); \
115 lw $9, PT_R9(sp); \
116 mtlo $24; \
117 lw $24, PT_HI(sp); \
118 lw $10,PT_R10(sp); \
119 lw $11, PT_R11(sp); \
120 mthi $24; \
121 lw $12, PT_R12(sp); \
122 lw $13, PT_R13(sp); \
123 lw $14, PT_R14(sp); \
124 lw $15, PT_R15(sp); \
125 lw $24, PT_R24(sp)
126
127 #define RESTORE_STATIC \
128 lw $16, PT_R16(sp); \
129 lw $17, PT_R17(sp); \
130 lw $18, PT_R18(sp); \
131 lw $19, PT_R19(sp); \
132 lw $20, PT_R20(sp); \
133 lw $21, PT_R21(sp); \
134 lw $22, PT_R22(sp); \
135 lw $23, PT_R23(sp); \
136 lw $30, PT_R30(sp)
137
138 #if defined(CONFIG_CPU_R3000)
139
140 #define RESTORE_SOME \
141 .set push; \
142 .set reorder; \
143 mfc0 t0, CP0_STATUS; \
144 .set pop; \
145 ori t0, 0x1f; \
146 xori t0, 0x1f; \
147 mtc0 t0, CP0_STATUS; \
148 li v1, 0xff00; \
149 and t0, v1; \
150 lw v0, PT_STATUS(sp); \
151 nor v1, $0, v1; \
152 and v0, v1; \
153 or v0, t0; \
154 mtc0 v0, CP0_STATUS; \
155 lw $31, PT_R31(sp); \
156 lw $28, PT_R28(sp); \
157 lw $25, PT_R25(sp); \
158 lw $7, PT_R7(sp); \
159 lw $6, PT_R6(sp); \
160 lw $5, PT_R5(sp); \
161 lw $4, PT_R4(sp); \
162 lw $3, PT_R3(sp); \
163 lw $2, PT_R2(sp)
164
165 #define RESTORE_SP_AND_RET \
166 .set push; \
167 .set noreorder; \
168 lw k0, PT_EPC(sp); \
169 lw sp, PT_R29(sp); \
170 jr k0; \
171 rfe; \
172 .set pop
173
174 #else
175
176 #define RESTORE_SOME \
177 .set push; \
178 .set reorder; \
179 mfc0 t0, CP0_STATUS; \
180 .set pop; \
181 ori t0, 0x1f; \
182 xori t0, 0x1f; \
183 mtc0 t0, CP0_STATUS; \
184 li v1, 0xff00; \
185 and t0, v1; \
186 lw v0, PT_STATUS(sp); \
187 nor v1, $0, v1; \
188 and v0, v1; \
189 or v0, t0; \
190 mtc0 v0, CP0_STATUS; \
191 lw v1, PT_EPC(sp); \
192 mtc0 v1, CP0_EPC; \
193 lw $31, PT_R31(sp); \
194 lw $28, PT_R28(sp); \
195 lw $25, PT_R25(sp); \
196 lw $7, PT_R7(sp); \
197 lw $6, PT_R6(sp); \
198 lw $5, PT_R5(sp); \
199 lw $4, PT_R4(sp); \
200 lw $3, PT_R3(sp); \
201 lw $2, PT_R2(sp)
202
203 #define RESTORE_SP_AND_RET \
204 lw sp, PT_R29(sp); \
205 .set mips3; \
206 eret; \
207 .set mips0
208
209 #endif
210
211 #define RESTORE_ALL_AND_RET \
212 RESTORE_SOME; \
213 RESTORE_AT; \
214 RESTORE_TEMP; \
215 RESTORE_STATIC; \
216 RESTORE_SP_AND_RET
217
218 /*
219 * Move to kernel mode and disable interrupts.
220 * Set cp0 enable bit as sign that we're running on the kernel stack
221 */
222 #define CLI \
223 mfc0 t0,CP0_STATUS; \
224 li t1,ST0_CU0|0x1f; \
225 or t0,t1; \
226 xori t0,0x1f; \
227 mtc0 t0,CP0_STATUS
228
229 /*
230 * Move to kernel mode and enable interrupts.
231 * Set cp0 enable bit as sign that we're running on the kernel stack
232 */
233 #define STI \
234 mfc0 t0,CP0_STATUS; \
235 li t1,ST0_CU0|0x1f; \
236 or t0,t1; \
237 xori t0,0x1e; \
238 mtc0 t0,CP0_STATUS
239
240 /*
241 * Just move to kernel mode and leave interrupts as they are.
242 * Set cp0 enable bit as sign that we're running on the kernel stack
243 */
244 #define KMODE \
245 mfc0 t0,CP0_STATUS; \
246 li t1,ST0_CU0|0x1e; \
247 or t0,t1; \
248 xori t0,0x1e; \
249 mtc0 t0,CP0_STATUS
250
251 #endif /* __ASM_MIPS_STACKFRAME_H */
252
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