1 /* $Id: asm.h,v 1.2 1999/12/04 03:59:12 ralf Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Copyright (C) 1995, 1996, 1997, 1999 by Ralf Baechle
8 * Copyright (C) 1999 by Silicon Graphics, Inc.
9 *
10 * Some useful macros for MIPS assembler code
11 *
12 * Some of the routines below contain useless nops that will be optimized
13 * away by gas in -O mode. These nops are however required to fill delay
14 * slots in noreorder mode.
15 */
16 #ifndef _ASM_ASM_H
17 #define _ASM_ASM_H
18
19 #include <asm/sgidefs.h>
20
21 /*
22 * PIC specific declarations
23 * Not used for the kernel but here seems to be the right place.
24 */
25 #ifdef __PIC__
26 #define CPRESTORE(register) \
27 .cprestore register
28 #define CPADD(register) \
29 .cpadd register
30 #define CPLOAD(register) \
31 .cpload register
32 #else
33 #define CPRESTORE(register)
34 #define CPADD(register)
35 #define CPLOAD(register)
36 #endif
37
38 /*
39 * LEAF - declare leaf routine
40 */
41 #define LEAF(symbol) \
42 .globl symbol; \
43 .align 2; \
44 .type symbol,@function; \
45 .ent symbol,0; \
46 symbol: .frame sp,0,ra
47
48 /*
49 * NESTED - declare nested routine entry point
50 */
51 #define NESTED(symbol, framesize, rpc) \
52 .globl symbol; \
53 .align 2; \
54 .type symbol,@function; \
55 .ent symbol,0; \
56 symbol: .frame sp, framesize, rpc
57
58 /*
59 * END - mark end of function
60 */
61 #define END(function) \
62 .end function; \
63 .size function,.-function
64
65 /*
66 * EXPORT - export definition of symbol
67 */
68 #define EXPORT(symbol) \
69 .globl symbol; \
70 symbol:
71
72 /*
73 * FEXPORT - export definition of a function symbol
74 */
75 #define FEXPORT(symbol) \
76 .globl symbol; \
77 .type symbol,@function; \
78 symbol:
79
80 /*
81 * ABS - export absolute symbol
82 */
83 #define ABS(symbol,value) \
84 .globl symbol; \
85 symbol = value
86
87 #define PANIC(msg) \
88 .set push; \
89 .set reorder; \
90 la a0,8f; \
91 jal panic; \
92 9: b 9b; \
93 .set pop; \
94 TEXT(msg)
95
96 /*
97 * Print formated string
98 */
99 #define PRINT(string) \
100 .set push; \
101 .set reorder; \
102 la a0,8f; \
103 jal printk; \
104 .set pop; \
105 TEXT(string)
106
107 /*
108 * Print formated string
109 */
110 #define PROM_PRINT(string) \
111 .set push; \
112 .set reorder; \
113 la a0,8f; \
114 jal prom_printf; \
115 .set pop; \
116 TEXT(string)
117
118 #define TEXT(msg) \
119 .data; \
120 8: .asciiz msg; \
121 .previous;
122
123 /*
124 * Build text tables
125 */
126 #define TTABLE(string) \
127 .text; \
128 .word 1f; \
129 .previous; \
130 .data; \
131 1: .asciz string; \
132 .previous
133
134 /*
135 * MIPS IV pref instruction.
136 * Use with .set noreorder only!
137 *
138 * MIPS IV implementations are free to treat this as a nop. The R5000
139 * is one of them. So we should have an option not to use this instruction.
140 */
141 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
142 #define PREF(hint,addr) \
143 pref hint,addr
144 #define PREFX(hint,addr) \
145 prefx hint,addr
146 #else
147 #define PREF
148 #define PREFX
149 #endif
150
151 /*
152 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
153 */
154 #if _MIPS_ISA == _MIPS_ISA_MIPS1
155 #define MOVN(rd,rs,rt) \
156 .set push; \
157 .set reorder; \
158 beqz rt,9f; \
159 move rd,rs; \
160 .set pop; \
161 9:
162 #define MOVZ(rd,rs,rt) \
163 .set push; \
164 .set reorder; \
165 bnez rt,9f; \
166 move rd,rt; \
167 .set pop; \
168 9:
169 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
170 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
171 #define MOVN(rd,rs,rt) \
172 .set push; \
173 .set noreorder; \
174 bnezl rt,9f; \
175 move rd,rs; \
176 .set pop; \
177 9:
178 #define MOVZ(rd,rs,rt) \
179 .set push; \
180 .set noreorder; \
181 beqzl rt,9f; \
182 movz rd,rs; \
183 .set pop; \
184 9:
185 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
186 #if (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5)
187 #define MOVN(rd,rs,rt) \
188 movn rd,rs,rt
189 #define MOVZ(rd,rs,rt) \
190 movz rd,rs,rt
191 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS4) || (_MIPS_ISA == _MIPS_ISA_MIPS5) */
192
193 /*
194 * Stack alignment
195 */
196 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
197 #define ALSZ 7
198 #define ALMASK ~7
199 #endif
200 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
201 (_MIPS_ISA == _MIPS_ISA_MIPS5)
202 #define ALSZ 15
203 #define ALMASK ~15
204 #endif
205
206 /*
207 * Size of a register
208 */
209 #ifdef __mips64
210 #define SZREG 8
211 #else
212 #define SZREG 4
213 #endif
214
215 /*
216 * Use the following macros in assemblercode to load/store registers,
217 * pointers etc.
218 */
219 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
220 #define REG_S sw
221 #define REG_L lw
222 #define PTR_SUBU dsubu
223 #define PTR_ADDU daddu
224 #endif
225 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
226 (_MIPS_ISA == _MIPS_ISA_MIPS5)
227 #define REG_S sd
228 #define REG_L ld
229 /* We still live in a 32 bit address space ... */
230 #define PTR_SUBU dsubu
231 #define PTR_ADDU daddu
232 #endif
233
234 /*
235 * How to add/sub/load/store/shift C int variables.
236 */
237 #if (_MIPS_SZINT == 32)
238 #define INT_ADD add
239 #define INT_ADDI addi
240 #define INT_ADDU addu
241 #define INT_ADDIU addiu
242 #define INT_SUB add
243 #define INT_SUBI subi
244 #define INT_SUBU subu
245 #define INT_SUBIU subu
246 #define INT_L lw
247 #define INT_S sw
248 #endif
249
250 #if (_MIPS_SZINT == 64)
251 #define INT_ADD dadd
252 #define INT_ADDI daddi
253 #define INT_ADDU daddu
254 #define INT_ADDIU daddiu
255 #define INT_SUB dadd
256 #define INT_SUBI dsubi
257 #define INT_SUBU dsubu
258 #define INT_SUBIU dsubu
259 #define INT_L ld
260 #define INT_S sd
261 #endif
262
263 /*
264 * How to add/sub/load/store/shift C long variables.
265 */
266 #if (_MIPS_SZLONG == 32)
267 #define LONG_ADD add
268 #define LONG_ADDI addi
269 #define LONG_ADDU addu
270 #define LONG_ADDIU addiu
271 #define LONG_SUB add
272 #define LONG_SUBI subi
273 #define LONG_SUBU subu
274 #define LONG_SUBIU subu
275 #define LONG_L lw
276 #define LONG_S sw
277 #define LONG_SLL sll
278 #define LONG_SLLV sllv
279 #define LONG_SRL srl
280 #define LONG_SRLV srlv
281 #define LONG_SRA sra
282 #define LONG_SRAV srav
283 #endif
284
285 #if (_MIPS_SZLONG == 64)
286 #define LONG_ADD dadd
287 #define LONG_ADDI daddi
288 #define LONG_ADDU daddu
289 #define LONG_ADDIU daddiu
290 #define LONG_SUB dadd
291 #define LONG_SUBI dsubi
292 #define LONG_SUBU dsubu
293 #define LONG_SUBIU dsubu
294 #define LONG_L ld
295 #define LONG_S sd
296 #define LONG_SLL dsll
297 #define LONG_SLLV dsllv
298 #define LONG_SRL dsrl
299 #define LONG_SRLV dsrlv
300 #define LONG_SRA dsra
301 #define LONG_SRAV dsrav
302 #endif
303
304 /*
305 * How to add/sub/load/store/shift pointers.
306 */
307 #if (_MIPS_SZPTR == 32)
308 #define PTR_ADD add
309 #define PTR_ADDI addi
310 #define PTR_ADDU addu
311 #define PTR_ADDIU addiu
312 #define PTR_SUB add
313 #define PTR_SUBI subi
314 #define PTR_SUBU subu
315 #define PTR_SUBIU subu
316 #define PTR_L lw
317 #define PTR_S sw
318 #define PTR_SLL sll
319 #define PTR_SLLV sllv
320 #define PTR_SRL srl
321 #define PTR_SRLV srlv
322 #define PTR_SRA sra
323 #define PTR_SRAV srav
324
325 #define PTR_SCALESHIFT 2
326
327 #define PTR .word
328 #define PTRSIZE 4
329 #define PTRLOG 2
330 #endif
331
332 #if (_MIPS_SZPTR == 64)
333 #define PTR_ADD dadd
334 #define PTR_ADDI daddi
335 #define PTR_ADDU daddu
336 #define PTR_ADDIU daddiu
337 #define PTR_SUB dadd
338 #define PTR_SUBI dsubi
339 #define PTR_SUBU dsubu
340 #define PTR_SUBIU dsubu
341 #define PTR_L ld
342 #define PTR_S sd
343 #define PTR_SLL dsll
344 #define PTR_SLLV dsllv
345 #define PTR_SRL dsrl
346 #define PTR_SRLV dsrlv
347 #define PTR_SRA dsra
348 #define PTR_SRAV dsrav
349
350 #define PTR_SCALESHIFT 3
351
352 #define PTR .dword
353 #define PTRSIZE 8
354 #define PTRLOG 3
355 #endif
356
357 /*
358 * Some cp0 registers were extended to 64bit for MIPS III.
359 */
360 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2)
361 #define MFC0 mfc0
362 #define MTC0 mtc0
363 #endif
364 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
365 (_MIPS_ISA == _MIPS_ISA_MIPS5)
366 #define MFC0 dmfc0
367 #define MTC0 dmtc0
368 #endif
369
370 #endif /* _ASM_ASM_H */
371
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