1 /* $Id: inst.h,v 1.1 1999/10/09 20:55:09 ralf Exp $
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Format of an instruction in memory.
8 *
9 * Copyright (C) 1996 by Ralf Baechle
10 */
11 #ifndef _ASM_INST_H
12 #define _ASM_INST_H
13
14 /*
15 * Major opcodes; before MIPS IV cop1x was called cop3.
16 */
17 enum major_op {
18 spec_op, bcond_op, j_op, jal_op,
19 beq_op, bne_op, blez_op, bgtz_op,
20 addi_op, addiu_op, slti_op, sltiu_op,
21 andi_op, ori_op, xori_op, lui_op,
22 cop0_op, cop1_op, cop2_op, cop1x_op,
23 beql_op, bnel_op, blezl_op, bgtzl_op,
24 daddi_op, daddiu_op, ldl_op, ldr_op,
25 major_1c_op, major_1d_op, major_1e_op, major_1f_op,
26 lb_op, lh_op, lwl_op, lw_op,
27 lbu_op, lhu_op, lwr_op, lwu_op,
28 sb_op, sh_op, swl_op, sw_op,
29 sdl_op, sdr_op, swr_op, cache_op,
30 ll_op, lwc1_op, lwc2_op, pref_op,
31 lld_op, ldc1_op, ldc2_op, ld_op,
32 sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
33 scd_op, sdc1_op, sdc2_op, sd_op
34 };
35
36 /*
37 * func field of spec opcode.
38 */
39 enum spec_op {
40 sll_op, movc_op, srl_op, sra_op,
41 sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
42 jr_op, jalr_op, movz_op, movn_op,
43 syscall_op, break_op, spim_op, sync_op,
44 mfhi_op, mthi_op, mflo_op, mtlo_op,
45 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
46 mult_op, multu_op, div_op, divu_op,
47 dmult_op, dmultu_op, ddiv_op, ddivu_op,
48 add_op, addu_op, sub_op, subu_op,
49 and_op, or_op, xor_op, nor_op,
50 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
51 dadd_op, daddu_op, dsub_op, dsubu_op,
52 tge_op, tgeu_op, tlt_op, tltu_op,
53 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
54 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
55 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
56 };
57
58 /*
59 * rt field of bcond opcodes.
60 */
61 enum rt_op {
62 bltz_op, bgez_op, bltzl_op, bgezl_op,
63 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
64 tgei_op, tgeiu_op, tlti_op, tltiu_op,
65 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
66 bltzal_op, bgezal_op, bltzall_op, bgezall_op
67 /*
68 * The others (0x14 - 0x1f) are unused.
69 */
70 };
71
72 /*
73 * rs field of cop opcodes.
74 */
75 enum cop_op {
76 mfc_op = 0x00, dmfc_op = 0x01,
77 cfc_op = 0x02, mtc_op = 0x04,
78 dmtc_op = 0x05, ctc_op = 0x06,
79 bc_op = 0x08, cop_op = 0x10,
80 copm_op = 0x18
81 };
82
83 /*
84 * func field of cop0 coi opcodes.
85 */
86 enum cop0_coi_func {
87 tlbr_op = 0x01, tlbwi_op = 0x02,
88 tlbwr_op = 0x06, tlbp_op = 0x08,
89 rfe_op = 0x10, eret_op = 0x18
90 };
91
92 /*
93 * func field of cop0 com opcodes.
94 */
95 enum cop0_com_func {
96 tlbr1_op = 0x01, tlbw_op = 0x02,
97 tlbp1_op = 0x08, dctr_op = 0x09,
98 dctw_op = 0x0a
99 };
100
101 /*
102 * fmt field of cop1 opcodes.
103 */
104 enum cop1_fmt {
105 s_fmt, d_fmt, e_fmt, q_fmt,
106 w_fmt, l_fmt
107 };
108
109 /*
110 * func field of cop1 instructions using d, s or w format.
111 */
112 enum cop1_sdw_func {
113 fadd_op = 0x00, fsub_op = 0x01,
114 fmul_op = 0x02, fdiv_op = 0x03,
115 fsqrt_op = 0x04, fabs_op = 0x05,
116 fmov_op = 0x06, fneg_op = 0x07,
117 froundl_op = 0x08, ftruncl_op = 0x09,
118 fceill_op = 0x0a, ffloorl_op = 0x0b,
119 fround_op = 0x0c, ftrunc_op = 0x0d,
120 fceil_op = 0x0e, ffloor_op = 0x0f,
121 fmovc_op = 0x11, fmovz_op = 0x12,
122 fmovn_op = 0x13, frecip_op = 0x15,
123 frsqrt_op = 0x16, fcvts_op = 0x20,
124 fcvtd_op = 0x21, fcvte_op = 0x22,
125 fcvtw_op = 0x24, fcvtl_op = 0x25,
126 fcmp_op = 0x30
127 };
128
129 /*
130 * func field of cop1x opcodes (MIPS IV).
131 */
132 enum cop1x_func {
133 lwxc1_op = 0x00, ldxc1_op = 0x01,
134 pfetch_op = 0x07, swxc1_op = 0x08,
135 sdxc1_op = 0x09, madd_s_op = 0x20,
136 madd_d_op = 0x21, madd_e_op = 0x22,
137 msub_s_op = 0x28, msub_d_op = 0x29,
138 msub_e_op = 0x2a, nmadd_s_op = 0x30,
139 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
140 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
141 nmsub_e_op = 0x3a
142 };
143
144 /*
145 * func field for mad opcodes (MIPS IV).
146 */
147 enum mad_func {
148 madd_op = 0x08, msub_op = 0x0a,
149 nmadd_op = 0x0c, nmsub_op = 0x0e
150 };
151
152 /*
153 * Damn ... bitfields depend from byteorder :-(
154 */
155 #ifdef __MIPSEB__
156 struct j_format { /* Jump format */
157 unsigned int opcode : 6;
158 unsigned int target : 26;
159 };
160
161 struct i_format { /* Immediate format (addi, lw, ...) */
162 unsigned int opcode : 6;
163 unsigned int rs : 5;
164 unsigned int rt : 5;
165 signed int simmediate : 16;
166 };
167
168 struct u_format { /* Unsigned immediate format (ori, xori, ...) */
169 unsigned int opcode : 6;
170 unsigned int rs : 5;
171 unsigned int rt : 5;
172 unsigned int uimmediate : 16;
173 };
174
175 struct c_format { /* Cache (>= R6000) format */
176 unsigned int opcode : 6;
177 unsigned int rs : 5;
178 unsigned int c_op : 3;
179 unsigned int cache : 2;
180 unsigned int simmediate : 16;
181 };
182
183 struct r_format { /* Register format */
184 unsigned int opcode : 6;
185 unsigned int rs : 5;
186 unsigned int rt : 5;
187 unsigned int rd : 5;
188 unsigned int re : 5;
189 unsigned int func : 6;
190 };
191
192 struct p_format { /* Performance counter format (R10000) */
193 unsigned int opcode : 6;
194 unsigned int rs : 5;
195 unsigned int rt : 5;
196 unsigned int rd : 5;
197 unsigned int re : 5;
198 unsigned int func : 6;
199 };
200
201 struct f_format { /* FPU register format */
202 unsigned int opcode : 6;
203 unsigned int : 1;
204 unsigned int fmt : 4;
205 unsigned int rt : 5;
206 unsigned int rd : 5;
207 unsigned int re : 5;
208 unsigned int func : 6;
209 };
210
211 struct ma_format { /* FPU multipy and add format (MIPS IV) */
212 unsigned int opcode : 6;
213 unsigned int fr : 5;
214 unsigned int ft : 5;
215 unsigned int fs : 5;
216 unsigned int fd : 5;
217 unsigned int func : 4;
218 unsigned int fmt : 2;
219 };
220
221 #elif defined(__MIPSEL__)
222
223 struct j_format { /* Jump format */
224 unsigned int target : 26;
225 unsigned int opcode : 6;
226 };
227
228 struct i_format { /* Immediate format */
229 signed int simmediate : 16;
230 unsigned int rt : 5;
231 unsigned int rs : 5;
232 unsigned int opcode : 6;
233 };
234
235 struct u_format { /* Unsigned immediate format */
236 unsigned int uimmediate : 16;
237 unsigned int rt : 5;
238 unsigned int rs : 5;
239 unsigned int opcode : 6;
240 };
241
242 struct c_format { /* Cache (>= R6000) format */
243 unsigned int simmediate : 16;
244 unsigned int cache : 2;
245 unsigned int c_op : 3;
246 unsigned int rs : 5;
247 unsigned int opcode : 6;
248 };
249
250 struct r_format { /* Register format */
251 unsigned int func : 6;
252 unsigned int re : 5;
253 unsigned int rd : 5;
254 unsigned int rt : 5;
255 unsigned int rs : 5;
256 unsigned int opcode : 6;
257 };
258
259 struct p_format { /* Performance counter format (R10000) */
260 unsigned int func : 6;
261 unsigned int re : 5;
262 unsigned int rd : 5;
263 unsigned int rt : 5;
264 unsigned int rs : 5;
265 unsigned int opcode : 6;
266 };
267
268 struct f_format { /* FPU register format */
269 unsigned int func : 6;
270 unsigned int re : 5;
271 unsigned int rd : 5;
272 unsigned int rt : 5;
273 unsigned int fmt : 4;
274 unsigned int : 1;
275 unsigned int opcode : 6;
276 };
277
278 struct ma_format { /* FPU multipy and add format (MIPS IV) */
279 unsigned int fmt : 2;
280 unsigned int func : 4;
281 unsigned int fd : 5;
282 unsigned int fs : 5;
283 unsigned int ft : 5;
284 unsigned int fr : 5;
285 unsigned int opcode : 6;
286 };
287
288 #else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
289 #error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
290 #endif
291
292 union mips_instruction {
293 unsigned int word;
294 unsigned short halfword[2];
295 unsigned char byte[4];
296 struct j_format j_format;
297 struct i_format i_format;
298 struct u_format u_format;
299 struct c_format c_format;
300 struct r_format r_format;
301 struct f_format f_format;
302 struct ma_format ma_format;
303 };
304
305 #endif /* _ASM_INST_H */
306
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