1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994 - 2000 by Ralf Baechle at alii
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9 #ifndef _ASM_PGTABLE_H
10 #define _ASM_PGTABLE_H
11
12 #include <asm/addrspace.h>
13 #include <asm/page.h>
14
15 #ifndef _LANGUAGE_ASSEMBLY
16
17 #include <linux/linkage.h>
18 #include <linux/config.h>
19 #include <linux/mmzone.h>
20 #include <asm/cachectl.h>
21
22 /* Cache flushing:
23 *
24 * - flush_cache_all() flushes entire cache
25 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
26 * - flush_cache_page(mm, vmaddr) flushes a single page
27 * - flush_cache_range(mm, start, end) flushes a range of pages
28 * - flush_page_to_ram(page) write back kernel page to ram
29 */
30 extern void (*_flush_cache_mm)(struct mm_struct *mm);
31 extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
32 unsigned long end);
33 extern void (*_flush_cache_page)(struct vm_area_struct *vma, unsigned long page);
34 extern void (*_flush_page_to_ram)(struct page * page);
35
36 #define flush_cache_all() do { } while(0)
37 #define flush_dcache_page(page) do { } while (0)
38
39 #ifndef CONFIG_CPU_R10000
40 #define flush_cache_mm(mm) _flush_cache_mm(mm)
41 #define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end)
42 #define flush_cache_page(vma,page) _flush_cache_page(vma, page)
43 #define flush_page_to_ram(page) _flush_page_to_ram(page)
44
45 #define flush_icache_range(start, end) _flush_cache_l1()
46
47 #define flush_icache_page(vma, page) \
48 do { \
49 unsigned long addr; \
50 addr = (unsigned long) page_address(page); \
51 _flush_cache_page(vma, addr); \
52 } while (0)
53 #else /* !CONFIG_CPU_R10000 */
54 /*
55 * Since the r10k handles VCEs in hardware, most of the flush cache
56 * routines are not needed. Only the icache on a processor is not
57 * coherent with the dcache of the _same_ processor, so we must flush
58 * the icache so that it does not contain stale contents of physical
59 * memory. No flushes are needed for dma coherency, since the o200s
60 * are io coherent. The only place where we might be overoptimizing
61 * out icache flushes are from mprotect (when PROT_EXEC is added).
62 */
63 extern void andes_flush_icache_page(unsigned long);
64 #define flush_cache_mm(mm) do { } while(0)
65 #define flush_cache_range(mm,start,end) do { } while(0)
66 #define flush_cache_page(vma,page) do { } while(0)
67 #define flush_page_to_ram(page) do { } while(0)
68 #define flush_icache_range(start, end) _flush_cache_l1()
69 #define flush_icache_page(vma, page) \
70 do { \
71 if ((vma)->vm_flags & VM_EXEC) \
72 andes_flush_icache_page(page_address(page)); \
73 } while (0)
74 #endif /* !CONFIG_CPU_R10000 */
75
76 /*
77 * The foll cache flushing routines are MIPS specific.
78 * flush_cache_l2 is needed only during initialization.
79 */
80 extern void (*_flush_cache_sigtramp)(unsigned long addr);
81 extern void (*_flush_cache_l2)(void);
82 extern void (*_flush_cache_l1)(void);
83
84 #define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr)
85 #define flush_cache_l2() _flush_cache_l2()
86 #define flush_cache_l1() _flush_cache_l1()
87
88 /*
89 * Each address space has 2 4K pages as its page directory, giving 1024
90 * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
91 * pair of 4K pages, giving 1024 (== PTRS_PER_PMD) 8 byte pointers to
92 * page tables. Each page table is a single 4K page, giving 512 (==
93 * PTRS_PER_PTE) 8 byte ptes. Each pgde is initialized to point to
94 * invalid_pmd_table, each pmde is initialized to point to
95 * invalid_pte_table, each pte is initialized to 0. When memory is low,
96 * and a pmd table or a page table allocation fails, empty_bad_pmd_table
97 * and empty_bad_page_table is returned back to higher layer code, so
98 * that the failure is recognized later on. Linux does not seem to
99 * handle these failures very well though. The empty_bad_page_table has
100 * invalid pte entries in it, to force page faults.
101 * Vmalloc handling: vmalloc uses swapper_pg_dir[0] (returned by
102 * pgd_offset_k), which is initalized to point to kpmdtbl. kpmdtbl is
103 * the only single page pmd in the system. kpmdtbl entries point into
104 * kptbl[] array. We reserve 1<<KPTBL_PAGE_ORDER pages to hold the
105 * vmalloc range translations, which the fault handler looks at.
106 */
107
108 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
109
110 /* PMD_SHIFT determines the size of the area a second-level page table can map */
111 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - 3))
112 #define PMD_SIZE (1UL << PMD_SHIFT)
113 #define PMD_MASK (~(PMD_SIZE-1))
114
115 /* PGDIR_SHIFT determines what a third-level page table entry can map */
116 #define PGDIR_SHIFT (PMD_SHIFT + (PAGE_SHIFT + 1 - 3))
117 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
118 #define PGDIR_MASK (~(PGDIR_SIZE-1))
119
120 /* Entries per page directory level: we use two-level, so we don't really
121 have any PMD directory physically. */
122 #define PTRS_PER_PGD 1024
123 #define PTRS_PER_PMD 1024
124 #define PTRS_PER_PTE 512
125 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
126 #define FIRST_USER_PGD_NR 0
127
128 #define KPTBL_PAGE_ORDER 1
129 #define VMALLOC_START XKSEG
130 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
131 #define VMALLOC_END \
132 (VMALLOC_START + ((1 << KPTBL_PAGE_ORDER) * PTRS_PER_PTE * PAGE_SIZE))
133
134 /* Note that we shift the lower 32bits of each EntryLo[01] entry
135 * 6 bits to the left. That way we can convert the PFN into the
136 * physical address by a single 'and' operation and gain 6 additional
137 * bits for storing information which isn't present in a normal
138 * MIPS page table.
139 *
140 * Similar to the Alpha port, we need to keep track of the ref
141 * and mod bits in software. We have a software "yeah you can read
142 * from this page" bit, and a hardware one which actually lets the
143 * process read from the page. On the same token we have a software
144 * writable bit and the real hardware one which actually lets the
145 * process write to the page, this keeps a mod bit via the hardware
146 * dirty bit.
147 *
148 * Certain revisions of the R4000 and R5000 have a bug where if a
149 * certain sequence occurs in the last 3 instructions of an executable
150 * page, and the following page is not mapped, the cpu can do
151 * unpredictable things. The code (when it is written) to deal with
152 * this problem will be in the update_mmu_cache() code for the r4k.
153 */
154 #define _PAGE_PRESENT (1<<0) /* implemented in software */
155 #define _PAGE_READ (1<<1) /* implemented in software */
156 #define _PAGE_WRITE (1<<2) /* implemented in software */
157 #define _PAGE_ACCESSED (1<<3) /* implemented in software */
158 #define _PAGE_MODIFIED (1<<4) /* implemented in software */
159 #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
160 #define _PAGE_GLOBAL (1<<6)
161 #define _PAGE_VALID (1<<7)
162 #define _PAGE_SILENT_READ (1<<7) /* synonym */
163 #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
164 #define _PAGE_SILENT_WRITE (1<<8)
165 #define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */
166 #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */
167 #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */
168 #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */
169 #define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00 only */
170 #define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00 only */
171 #define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00 only */
172 #define _CACHE_CACHABLE_ACCELERATED (7<<9) /* R10000 only */
173 #define _CACHE_MASK (7<<9)
174
175 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
176 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
177
178 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
179
180 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_COW)
181 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
182 _CACHE_CACHABLE_COW)
183 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
184 _CACHE_CACHABLE_COW)
185 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
186 _CACHE_CACHABLE_COW)
187 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
188 _CACHE_CACHABLE_COW)
189 #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
190 _CACHE_UNCACHED)
191 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
192 _CACHE_UNCACHED)
193
194 /*
195 * MIPS can't do page protection for execute, and considers that the same like
196 * read. Also, write permissions imply read permissions. This is the closest
197 * we can get by reasonable means..
198 */
199 #define __P000 PAGE_NONE
200 #define __P001 PAGE_READONLY
201 #define __P010 PAGE_COPY
202 #define __P011 PAGE_COPY
203 #define __P100 PAGE_READONLY
204 #define __P101 PAGE_READONLY
205 #define __P110 PAGE_COPY
206 #define __P111 PAGE_COPY
207
208 #define __S000 PAGE_NONE
209 #define __S001 PAGE_READONLY
210 #define __S010 PAGE_SHARED
211 #define __S011 PAGE_SHARED
212 #define __S100 PAGE_READONLY
213 #define __S101 PAGE_READONLY
214 #define __S110 PAGE_SHARED
215 #define __S111 PAGE_SHARED
216
217 #if !defined (_LANGUAGE_ASSEMBLY)
218
219 #define pte_ERROR(e) \
220 printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
221 #define pmd_ERROR(e) \
222 printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
223 #define pgd_ERROR(e) \
224 printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
225
226 /*
227 * BAD_PAGETABLE is used when we need a bogus page-table, while
228 * BAD_PAGE is used for a bogus page.
229 *
230 * ZERO_PAGE is a global shared page that is always zero: used
231 * for zero-mapped memory areas etc..
232 */
233 extern pte_t __bad_page(void);
234 extern pte_t *__bad_pagetable(void);
235 extern pmd_t *__bad_pmd_table(void);
236
237 extern unsigned long empty_zero_page;
238 extern unsigned long zero_page_mask;
239
240 #define BAD_PAGETABLE __bad_pagetable()
241 #define BAD_PMDTABLE __bad_pmd_table()
242 #define BAD_PAGE __bad_page()
243 #define ZERO_PAGE(vaddr) \
244 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
245
246 /* number of bits that fit into a memory pointer */
247 #define BITS_PER_PTR (8*sizeof(unsigned long))
248
249 /* to align the pointer to a pointer address */
250 #define PTR_MASK (~(sizeof(void*)-1))
251
252 /*
253 * sizeof(void*) == (1 << SIZEOF_PTR_LOG2)
254 */
255 #define SIZEOF_PTR_LOG2 3
256
257 /* to find an entry in a page-table */
258 #define PAGE_PTR(address) \
259 ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
260
261 extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
262 extern pte_t empty_bad_page_table[PAGE_SIZE/sizeof(pte_t)];
263 extern pmd_t invalid_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
264 extern pmd_t empty_bad_pmd_table[2*PAGE_SIZE/sizeof(pmd_t)];
265
266 /*
267 * Conversion functions: convert a page and protection to a page entry,
268 * and a page entry and page directory to the page they refer to.
269 */
270 extern inline unsigned long pmd_page(pmd_t pmd)
271 {
272 return pmd_val(pmd);
273 }
274
275 extern inline unsigned long pgd_page(pgd_t pgd)
276 {
277 return pgd_val(pgd);
278 }
279
280 extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
281 {
282 pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
283 }
284
285 extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
286 {
287 pgd_val(*pgdp) = (((unsigned long) pmdp) & PAGE_MASK);
288 }
289
290 extern inline int pte_none(pte_t pte)
291 {
292 return !pte_val(pte);
293 }
294
295 extern inline int pte_present(pte_t pte)
296 {
297 return pte_val(pte) & _PAGE_PRESENT;
298 }
299
300 /* Certain architectures need to do special things when pte's
301 * within a page table are directly modified. Thus, the following
302 * hook is made available.
303 */
304 extern inline void set_pte(pte_t *ptep, pte_t pteval)
305 {
306 *ptep = pteval;
307 }
308
309 extern inline void pte_clear(pte_t *ptep)
310 {
311 set_pte(ptep, __pte(0));
312 }
313
314 /*
315 * Empty pmd entries point to the invalid_pte_table.
316 */
317 extern inline int pmd_none(pmd_t pmd)
318 {
319 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
320 }
321
322 extern inline int pmd_bad(pmd_t pmd)
323 {
324 return pmd_val(pmd) == (unsigned long) empty_bad_page_table;
325 }
326
327 extern inline void pmd_clear(pmd_t *pmdp)
328 {
329 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
330 }
331
332 /*
333 * Empty pgd entries point to the invalid_pmd_table.
334 */
335 extern inline int pgd_none(pgd_t pgd)
336 {
337 return pgd_val(pgd) == (unsigned long) invalid_pmd_table;
338 }
339
340 extern inline int pgd_bad(pgd_t pgd)
341 {
342 return pgd_val(pgd) == (unsigned long) empty_bad_pmd_table;
343 }
344
345 extern inline void pgd_clear(pgd_t *pgdp)
346 {
347 pgd_val(*pgdp) = ((unsigned long) invalid_pmd_table);
348 }
349
350 /*
351 * Permanent address of a page. On MIPS64 we never have highmem, so this
352 * is simple.
353 * called on a highmem page.
354 */
355 #define page_address(page) ((page)->virtual)
356 #ifndef CONFIG_DISCONTIGMEM
357 #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
358 #else
359 #define mips64_pte_pagenr(x) \
360 (PLAT_NODE_DATA_STARTNR(PHYSADDR_TO_NID(pte_val(x))) + \
361 PLAT_NODE_DATA_LOCALNR(pte_val(x), PHYSADDR_TO_NID(pte_val(x))))
362 #define pte_page(x) (mem_map+mips64_pte_pagenr(x))
363 #endif
364
365 /*
366 * The following only work if pte_present() is true.
367 * Undefined behaviour if not..
368 */
369 extern inline int pte_read(pte_t pte)
370 {
371 return pte_val(pte) & _PAGE_READ;
372 }
373
374 extern inline int pte_write(pte_t pte)
375 {
376 return pte_val(pte) & _PAGE_WRITE;
377 }
378
379 extern inline int pte_dirty(pte_t pte)
380 {
381 return pte_val(pte) & _PAGE_MODIFIED;
382 }
383
384 extern inline int pte_young(pte_t pte)
385 {
386 return pte_val(pte) & _PAGE_ACCESSED;
387 }
388
389 extern inline pte_t pte_wrprotect(pte_t pte)
390 {
391 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
392 return pte;
393 }
394
395 extern inline pte_t pte_rdprotect(pte_t pte)
396 {
397 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
398 return pte;
399 }
400
401 extern inline pte_t pte_mkclean(pte_t pte)
402 {
403 pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
404 return pte;
405 }
406
407 extern inline pte_t pte_mkold(pte_t pte)
408 {
409 pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
410 return pte;
411 }
412
413 extern inline pte_t pte_mkwrite(pte_t pte)
414 {
415 pte_val(pte) |= _PAGE_WRITE;
416 if (pte_val(pte) & _PAGE_MODIFIED)
417 pte_val(pte) |= _PAGE_SILENT_WRITE;
418 return pte;
419 }
420
421 extern inline pte_t pte_mkread(pte_t pte)
422 {
423 pte_val(pte) |= _PAGE_READ;
424 if (pte_val(pte) & _PAGE_ACCESSED)
425 pte_val(pte) |= _PAGE_SILENT_READ;
426 return pte;
427 }
428
429 extern inline pte_t pte_mkdirty(pte_t pte)
430 {
431 pte_val(pte) |= _PAGE_MODIFIED;
432 if (pte_val(pte) & _PAGE_WRITE)
433 pte_val(pte) |= _PAGE_SILENT_WRITE;
434 return pte;
435 }
436
437 extern inline pte_t pte_mkyoung(pte_t pte)
438 {
439 pte_val(pte) |= _PAGE_ACCESSED;
440 if (pte_val(pte) & _PAGE_READ)
441 pte_val(pte) |= _PAGE_SILENT_READ;
442 return pte;
443 }
444
445 /*
446 * Conversion functions: convert a page and protection to a page entry,
447 * and a page entry and page directory to the page they refer to.
448 */
449 #ifndef CONFIG_DISCONTIGMEM
450 #define PAGE_TO_PA(page) ((page - mem_map) << PAGE_SHIFT)
451 #else
452 #define PAGE_TO_PA(page) \
453 ((((page)-(page)->zone->zone_mem_map) << PAGE_SHIFT) \
454 + ((page)->zone->zone_start_paddr))
455 #endif
456 #define mk_pte(page, pgprot) \
457 ({ \
458 pte_t __pte; \
459 \
460 pte_val(__pte) = ((unsigned long)(PAGE_TO_PA(page))) | \
461 pgprot_val(pgprot); \
462 \
463 __pte; \
464 })
465
466 extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
467 {
468 return __pte(physpage | pgprot_val(pgprot));
469 }
470
471 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
472 {
473 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
474 }
475
476 #define page_pte(page) page_pte_prot(page, __pgprot(0))
477
478 /* to find an entry in a kernel page-table-directory */
479 #define pgd_offset_k(address) pgd_offset(&init_mm, 0)
480
481 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
482
483 /* to find an entry in a page-table-directory */
484 extern inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
485 {
486 return mm->pgd + pgd_index(address);
487 }
488
489 /* Find an entry in the second-level page table.. */
490 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
491 {
492 return (pmd_t *) pgd_page(*dir) +
493 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
494 }
495
496 /* Find an entry in the third-level page table.. */
497 extern inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
498 {
499 return (pte_t *) (pmd_page(*dir)) +
500 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
501 }
502
503 /*
504 * Initialize a new pgd / pmd table with invalid pointers.
505 */
506 extern void pgd_init(unsigned long page);
507 extern void pmd_init(unsigned long page, unsigned long pagetable);
508
509 extern pgd_t swapper_pg_dir[1024];
510 extern void paging_init(void);
511
512 extern void (*update_mmu_cache)(struct vm_area_struct *vma,
513 unsigned long address, pte_t pte);
514
515 /*
516 * Non-present pages: high 24 bits are offset, next 8 bits type,
517 * low 32 bits zero.
518 */
519 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
520 { pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
521
522 #define SWP_TYPE(x) (((x).val >> 32) & 0xff)
523 #define SWP_OFFSET(x) ((x).val >> 40)
524 #define SWP_ENTRY(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
525 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
526 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
527
528 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
529 #define PageSkip(page) (0)
530 #ifndef CONFIG_DISCONTIGMEM
531 #define kern_addr_valid(addr) (1)
532 #endif
533
534 /* TLB operations. */
535 extern inline void tlb_probe(void)
536 {
537 __asm__ __volatile__(
538 ".set noreorder\n\t"
539 "tlbp\n\t"
540 ".set reorder");
541 }
542
543 extern inline void tlb_read(void)
544 {
545 __asm__ __volatile__(
546 ".set noreorder\n\t"
547 "tlbr\n\t"
548 ".set reorder");
549 }
550
551 extern inline void tlb_write_indexed(void)
552 {
553 __asm__ __volatile__(
554 ".set noreorder\n\t"
555 "tlbwi\n\t"
556 ".set reorder");
557 }
558
559 extern inline void tlb_write_random(void)
560 {
561 __asm__ __volatile__(
562 ".set noreorder\n\t"
563 "tlbwr\n\t"
564 ".set reorder");
565 }
566
567 /* Dealing with various CP0 mmu/cache related registers. */
568
569 /* CP0_PAGEMASK register */
570 extern inline unsigned long get_pagemask(void)
571 {
572 unsigned long val;
573
574 __asm__ __volatile__(
575 ".set noreorder\n\t"
576 "mfc0 %0, $5\n\t"
577 ".set reorder"
578 : "=r" (val));
579 return val;
580 }
581
582 extern inline void set_pagemask(unsigned long val)
583 {
584 __asm__ __volatile__(
585 ".set noreorder\n\t"
586 "mtc0 %0, $5\n\t"
587 ".set reorder"
588 : : "r" (val));
589 }
590
591 /* CP0_ENTRYLO0 and CP0_ENTRYLO1 registers */
592 extern inline unsigned long get_entrylo0(void)
593 {
594 unsigned long val;
595
596 __asm__ __volatile__(
597 ".set noreorder\n\t"
598 "dmfc0 %0, $2\n\t"
599 ".set reorder"
600 : "=r" (val));
601 return val;
602 }
603
604 extern inline void set_entrylo0(unsigned long val)
605 {
606 __asm__ __volatile__(
607 ".set noreorder\n\t"
608 "dmtc0 %0, $2\n\t"
609 ".set reorder"
610 : : "r" (val));
611 }
612
613 extern inline unsigned long get_entrylo1(void)
614 {
615 unsigned long val;
616
617 __asm__ __volatile__(
618 ".set noreorder\n\t"
619 "dmfc0 %0, $3\n\t"
620 ".set reorder" : "=r" (val));
621
622 return val;
623 }
624
625 extern inline void set_entrylo1(unsigned long val)
626 {
627 __asm__ __volatile__(
628 ".set noreorder\n\t"
629 "dmtc0 %0, $3\n\t"
630 ".set reorder"
631 : : "r" (val));
632 }
633
634 /* CP0_ENTRYHI register */
635 extern inline unsigned long get_entryhi(void)
636 {
637 unsigned long val;
638
639 __asm__ __volatile__(
640 ".set noreorder\n\t"
641 "dmfc0 %0, $10\n\t"
642 ".set reorder"
643 : "=r" (val));
644
645 return val;
646 }
647
648 extern inline void set_entryhi(unsigned long val)
649 {
650 __asm__ __volatile__(
651 ".set noreorder\n\t"
652 "dmtc0 %0, $10\n\t"
653 ".set reorder"
654 : : "r" (val));
655 }
656
657 /* CP0_INDEX register */
658 extern inline unsigned int get_index(void)
659 {
660 unsigned long val;
661
662 __asm__ __volatile__(
663 ".set noreorder\n\t"
664 "mfc0 %0, $0\n\t"
665 ".set reorder"
666 : "=r" (val));
667 return val;
668 }
669
670 extern inline void set_index(unsigned int val)
671 {
672 __asm__ __volatile__(
673 ".set noreorder\n\t"
674 "mtc0 %0, $0\n\t"
675 ".set reorder\n\t"
676 : : "r" (val));
677 }
678
679 /* CP0_WIRED register */
680 extern inline unsigned long get_wired(void)
681 {
682 unsigned long val;
683
684 __asm__ __volatile__(
685 ".set noreorder\n\t"
686 "mfc0 %0, $6\n\t"
687 ".set reorder\n\t"
688 : "=r" (val));
689 return val;
690 }
691
692 extern inline void set_wired(unsigned long val)
693 {
694 __asm__ __volatile__(
695 "\n\t.set noreorder\n\t"
696 "mtc0 %0, $6\n\t"
697 ".set reorder"
698 : : "r" (val));
699 }
700
701 extern inline unsigned long get_info(void)
702 {
703 unsigned long val;
704
705 __asm__(
706 ".set push\n\t"
707 ".set reorder\n\t"
708 "mfc0 %0, $7\n\t"
709 ".set pop"
710 : "=r" (val));
711 return val;
712 }
713
714 /* CP0_TAGLO and CP0_TAGHI registers */
715 extern inline unsigned long get_taglo(void)
716 {
717 unsigned long val;
718
719 __asm__ __volatile__(
720 ".set noreorder\n\t"
721 "mfc0 %0, $28\n\t"
722 ".set reorder"
723 : "=r" (val));
724 return val;
725 }
726
727 extern inline void set_taglo(unsigned long val)
728 {
729 __asm__ __volatile__(
730 ".set noreorder\n\t"
731 "mtc0 %0, $28\n\t"
732 ".set reorder"
733 : : "r" (val));
734 }
735
736 extern inline unsigned long get_taghi(void)
737 {
738 unsigned long val;
739
740 __asm__ __volatile__(
741 ".set noreorder\n\t"
742 "mfc0 %0, $29\n\t"
743 ".set reorder"
744 : "=r" (val));
745 return val;
746 }
747
748 extern inline void set_taghi(unsigned long val)
749 {
750 __asm__ __volatile__(
751 ".set noreorder\n\t"
752 "mtc0 %0, $29\n\t"
753 ".set reorder"
754 : : "r" (val));
755 }
756
757 /* CP0_CONTEXT register */
758 extern inline unsigned long get_context(void)
759 {
760 unsigned long val;
761
762 __asm__ __volatile__(
763 ".set noreorder\n\t"
764 "mfc0 %0, $4\n\t"
765 ".set reorder"
766 : "=r" (val));
767
768 return val;
769 }
770
771 extern inline void set_context(unsigned long val)
772 {
773 __asm__ __volatile__(
774 ".set noreorder\n\t"
775 "mtc0 %0, $4\n\t"
776 ".set reorder"
777 : : "r" (val));
778 }
779
780 #include <asm-generic/pgtable.h>
781
782 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
783
784 #endif /* _ASM_PGTABLE_H */
785
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