1 /* $Id$
2 *
3 * This file is subject to the terms and conditions of the GNU General Public
4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details.
6 *
7 * Inline assembly cache operations.
8 *
9 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
10 *
11 * FIXME: Handle split L2 caches.
12 */
13 #ifndef _ASM_R4KCACHE_H
14 #define _ASM_R4KCACHE_H
15
16 #include <asm/asm.h>
17 #include <asm/r4kcacheops.h>
18
19 extern inline void flush_icache_line_indexed(unsigned long addr)
20 {
21 __asm__ __volatile__(
22 ".set noreorder\n\t"
23 "cache %1, (%0)\n\t"
24 ".set reorder"
25 :
26 : "r" (addr), "i" (Index_Invalidate_I));
27 }
28
29 extern inline void flush_dcache_line_indexed(unsigned long addr)
30 {
31 __asm__ __volatile__(
32 ".set noreorder\n\t"
33 "cache %1, (%0)\n\t"
34 ".set reorder"
35 :
36 : "r" (addr), "i" (Index_Writeback_Inv_D));
37 }
38
39 extern inline void flush_scache_line_indexed(unsigned long addr)
40 {
41 __asm__ __volatile__(
42 ".set noreorder\n\t"
43 "cache %1, (%0)\n\t"
44 ".set reorder"
45 :
46 : "r" (addr), "i" (Index_Writeback_Inv_SD));
47 }
48
49 extern inline void flush_icache_line(unsigned long addr)
50 {
51 __asm__ __volatile__(
52 ".set noreorder\n\t"
53 "cache %1, (%0)\n\t"
54 ".set reorder"
55 :
56 : "r" (addr), "i" (Hit_Invalidate_I));
57 }
58
59 extern inline void flush_dcache_line(unsigned long addr)
60 {
61 __asm__ __volatile__(
62 ".set noreorder\n\t"
63 "cache %1, (%0)\n\t"
64 ".set reorder"
65 :
66 : "r" (addr), "i" (Hit_Writeback_Inv_D));
67 }
68
69 extern inline void invalidate_dcache_line(unsigned long addr)
70 {
71 __asm__ __volatile__(
72 ".set noreorder\n\t"
73 "cache %1, (%0)\n\t"
74 ".set reorder"
75 :
76 : "r" (addr), "i" (Hit_Invalidate_D));
77 }
78
79 extern inline void invalidate_scache_line(unsigned long addr)
80 {
81 __asm__ __volatile__(
82 ".set noreorder\n\t"
83 "cache %1, (%0)\n\t"
84 ".set reorder"
85 :
86 : "r" (addr), "i" (Hit_Invalidate_SD));
87 }
88
89 extern inline void flush_scache_line(unsigned long addr)
90 {
91 __asm__ __volatile__(
92 ".set noreorder\n\t"
93 "cache %1, (%0)\n\t"
94 ".set reorder"
95 :
96 : "r" (addr), "i" (Hit_Writeback_Inv_SD));
97 }
98
99 /*
100 * The next two are for badland addresses like signal trampolines.
101 */
102 extern inline void protected_flush_icache_line(unsigned long addr)
103 {
104 __asm__ __volatile__(
105 ".set noreorder\n\t"
106 "1:\tcache %1,(%0)\n"
107 "2:\t.set reorder\n\t"
108 ".section\t__ex_table,\"a\"\n\t"
109 ".dword\t1b,2b\n\t"
110 ".previous"
111 :
112 : "r" (addr), "i" (Hit_Invalidate_I));
113 }
114
115 extern inline void protected_writeback_dcache_line(unsigned long addr)
116 {
117 __asm__ __volatile__(
118 ".set noreorder\n\t"
119 "1:\tcache %1,(%0)\n"
120 "2:\t.set reorder\n\t"
121 ".section\t__ex_table,\"a\"\n\t"
122 ".dword\t1b,2b\n\t"
123 ".previous"
124 :
125 : "r" (addr), "i" (Hit_Writeback_D));
126 }
127
128 #define cache16_unroll32(base,op) \
129 __asm__ __volatile__(" \
130 .set noreorder; \
131 cache %1, 0x000(%0); cache %1, 0x010(%0); \
132 cache %1, 0x020(%0); cache %1, 0x030(%0); \
133 cache %1, 0x040(%0); cache %1, 0x050(%0); \
134 cache %1, 0x060(%0); cache %1, 0x070(%0); \
135 cache %1, 0x080(%0); cache %1, 0x090(%0); \
136 cache %1, 0x0a0(%0); cache %1, 0x0b0(%0); \
137 cache %1, 0x0c0(%0); cache %1, 0x0d0(%0); \
138 cache %1, 0x0e0(%0); cache %1, 0x0f0(%0); \
139 cache %1, 0x100(%0); cache %1, 0x110(%0); \
140 cache %1, 0x120(%0); cache %1, 0x130(%0); \
141 cache %1, 0x140(%0); cache %1, 0x150(%0); \
142 cache %1, 0x160(%0); cache %1, 0x170(%0); \
143 cache %1, 0x180(%0); cache %1, 0x190(%0); \
144 cache %1, 0x1a0(%0); cache %1, 0x1b0(%0); \
145 cache %1, 0x1c0(%0); cache %1, 0x1d0(%0); \
146 cache %1, 0x1e0(%0); cache %1, 0x1f0(%0); \
147 .set reorder" \
148 : \
149 : "r" (base), \
150 "i" (op));
151
152 extern inline void blast_dcache16(void)
153 {
154 unsigned long start = KSEG0;
155 unsigned long end = (start + dcache_size);
156
157 while(start < end) {
158 cache16_unroll32(start,Index_Writeback_Inv_D);
159 start += 0x200;
160 }
161 }
162
163 extern inline void blast_dcache16_page(unsigned long page)
164 {
165 unsigned long start = page;
166 unsigned long end = (start + PAGE_SIZE);
167
168 while(start < end) {
169 cache16_unroll32(start,Hit_Writeback_Inv_D);
170 start += 0x200;
171 }
172 }
173
174 extern inline void blast_dcache16_page_indexed(unsigned long page)
175 {
176 unsigned long start = page;
177 unsigned long end = (start + PAGE_SIZE);
178
179 while(start < end) {
180 cache16_unroll32(start,Index_Writeback_Inv_D);
181 start += 0x200;
182 }
183 }
184
185 extern inline void blast_icache16(void)
186 {
187 unsigned long start = KSEG0;
188 unsigned long end = (start + icache_size);
189
190 while(start < end) {
191 cache16_unroll32(start,Index_Invalidate_I);
192 start += 0x200;
193 }
194 }
195
196 extern inline void blast_icache16_page(unsigned long page)
197 {
198 unsigned long start = page;
199 unsigned long end = (start + PAGE_SIZE);
200
201 while(start < end) {
202 cache16_unroll32(start,Hit_Invalidate_I);
203 start += 0x200;
204 }
205 }
206
207 extern inline void blast_icache16_page_indexed(unsigned long page)
208 {
209 unsigned long start = page;
210 unsigned long end = (start + PAGE_SIZE);
211
212 while(start < end) {
213 cache16_unroll32(start,Index_Invalidate_I);
214 start += 0x200;
215 }
216 }
217
218 extern inline void blast_scache16(void)
219 {
220 unsigned long start = KSEG0;
221 unsigned long end = KSEG0 + scache_size;
222
223 while(start < end) {
224 cache16_unroll32(start,Index_Writeback_Inv_SD);
225 start += 0x200;
226 }
227 }
228
229 extern inline void blast_scache16_page(unsigned long page)
230 {
231 unsigned long start = page;
232 unsigned long end = page + PAGE_SIZE;
233
234 while(start < end) {
235 cache16_unroll32(start,Hit_Writeback_Inv_SD);
236 start += 0x200;
237 }
238 }
239
240 extern inline void blast_scache16_page_indexed(unsigned long page)
241 {
242 unsigned long start = page;
243 unsigned long end = page + PAGE_SIZE;
244
245 while(start < end) {
246 cache16_unroll32(start,Index_Writeback_Inv_SD);
247 start += 0x200;
248 }
249 }
250
251 #define cache32_unroll32(base,op) \
252 __asm__ __volatile__(" \
253 .set noreorder; \
254 cache %1, 0x000(%0); cache %1, 0x020(%0); \
255 cache %1, 0x040(%0); cache %1, 0x060(%0); \
256 cache %1, 0x080(%0); cache %1, 0x0a0(%0); \
257 cache %1, 0x0c0(%0); cache %1, 0x0e0(%0); \
258 cache %1, 0x100(%0); cache %1, 0x120(%0); \
259 cache %1, 0x140(%0); cache %1, 0x160(%0); \
260 cache %1, 0x180(%0); cache %1, 0x1a0(%0); \
261 cache %1, 0x1c0(%0); cache %1, 0x1e0(%0); \
262 cache %1, 0x200(%0); cache %1, 0x220(%0); \
263 cache %1, 0x240(%0); cache %1, 0x260(%0); \
264 cache %1, 0x280(%0); cache %1, 0x2a0(%0); \
265 cache %1, 0x2c0(%0); cache %1, 0x2e0(%0); \
266 cache %1, 0x300(%0); cache %1, 0x320(%0); \
267 cache %1, 0x340(%0); cache %1, 0x360(%0); \
268 cache %1, 0x380(%0); cache %1, 0x3a0(%0); \
269 cache %1, 0x3c0(%0); cache %1, 0x3e0(%0); \
270 .set reorder" \
271 : \
272 : "r" (base), \
273 "i" (op));
274
275 extern inline void blast_dcache32(void)
276 {
277 unsigned long start = KSEG0;
278 unsigned long end = (start + dcache_size);
279
280 while(start < end) {
281 cache32_unroll32(start,Index_Writeback_Inv_D);
282 start += 0x400;
283 }
284 }
285
286 /*
287 * Call this function only with interrupts disabled or R4600 V2.0 may blow
288 * up on you.
289 *
290 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
291 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Excl_D will only
292 * operate correctly if the internal data cache refill buffer is empty. These
293 * CACHE instructions should be separated from any potential data cache miss
294 * by a load instruction to an uncached address to empty the response buffer."
295 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
296 * in .pdf format.)
297 */
298 extern inline void blast_dcache32_page(unsigned long page)
299 {
300 unsigned long start = page;
301 unsigned long end = (start + PAGE_SIZE);
302
303 /*
304 * Sigh ... workaround for R4600 v1.7 bug. Explanation see above.
305 */
306 *(volatile unsigned long *)KSEG1;
307
308 __asm__ __volatile__("nop;nop;nop;nop");
309 while(start < end) {
310 cache32_unroll32(start,Hit_Writeback_Inv_D);
311 start += 0x400;
312 }
313 }
314
315 extern inline void blast_dcache32_page_indexed(unsigned long page)
316 {
317 unsigned long start = page;
318 unsigned long end = (start + PAGE_SIZE);
319
320 while(start < end) {
321 cache32_unroll32(start,Index_Writeback_Inv_D);
322 start += 0x400;
323 }
324 }
325
326 extern inline void blast_icache32(void)
327 {
328 unsigned long start = KSEG0;
329 unsigned long end = (start + icache_size);
330
331 while(start < end) {
332 cache32_unroll32(start,Index_Invalidate_I);
333 start += 0x400;
334 }
335 }
336
337 extern inline void blast_icache32_page(unsigned long page)
338 {
339 unsigned long start = page;
340 unsigned long end = (start + PAGE_SIZE);
341
342 while(start < end) {
343 cache32_unroll32(start,Hit_Invalidate_I);
344 start += 0x400;
345 }
346 }
347
348 extern inline void blast_icache32_page_indexed(unsigned long page)
349 {
350 unsigned long start = page;
351 unsigned long end = (start + PAGE_SIZE);
352
353 while(start < end) {
354 cache32_unroll32(start,Index_Invalidate_I);
355 start += 0x400;
356 }
357 }
358
359 extern inline void blast_scache32(void)
360 {
361 unsigned long start = KSEG0;
362 unsigned long end = KSEG0 + scache_size;
363
364 while(start < end) {
365 cache32_unroll32(start,Index_Writeback_Inv_SD);
366 start += 0x400;
367 }
368 }
369
370 extern inline void blast_scache32_page(unsigned long page)
371 {
372 unsigned long start = page;
373 unsigned long end = page + PAGE_SIZE;
374
375 while(start < end) {
376 cache32_unroll32(start,Hit_Writeback_Inv_SD);
377 start += 0x400;
378 }
379 }
380
381 extern inline void blast_scache32_page_indexed(unsigned long page)
382 {
383 unsigned long start = page;
384 unsigned long end = page + PAGE_SIZE;
385
386 while(start < end) {
387 cache32_unroll32(start,Index_Writeback_Inv_SD);
388 start += 0x400;
389 }
390 }
391
392 #define cache64_unroll32(base,op) \
393 __asm__ __volatile__(" \
394 .set noreorder; \
395 cache %1, 0x000(%0); cache %1, 0x040(%0); \
396 cache %1, 0x080(%0); cache %1, 0x0c0(%0); \
397 cache %1, 0x100(%0); cache %1, 0x140(%0); \
398 cache %1, 0x180(%0); cache %1, 0x1c0(%0); \
399 cache %1, 0x200(%0); cache %1, 0x240(%0); \
400 cache %1, 0x280(%0); cache %1, 0x2c0(%0); \
401 cache %1, 0x300(%0); cache %1, 0x340(%0); \
402 cache %1, 0x380(%0); cache %1, 0x3c0(%0); \
403 cache %1, 0x400(%0); cache %1, 0x440(%0); \
404 cache %1, 0x480(%0); cache %1, 0x4c0(%0); \
405 cache %1, 0x500(%0); cache %1, 0x540(%0); \
406 cache %1, 0x580(%0); cache %1, 0x5c0(%0); \
407 cache %1, 0x600(%0); cache %1, 0x640(%0); \
408 cache %1, 0x680(%0); cache %1, 0x6c0(%0); \
409 cache %1, 0x700(%0); cache %1, 0x740(%0); \
410 cache %1, 0x780(%0); cache %1, 0x7c0(%0); \
411 .set reorder" \
412 : \
413 : "r" (base), \
414 "i" (op));
415
416 extern inline void blast_scache64(void)
417 {
418 unsigned long start = KSEG0;
419 unsigned long end = KSEG0 + scache_size;
420
421 while(start < end) {
422 cache64_unroll32(start,Index_Writeback_Inv_SD);
423 start += 0x800;
424 }
425 }
426
427 extern inline void blast_scache64_page(unsigned long page)
428 {
429 unsigned long start = page;
430 unsigned long end = page + PAGE_SIZE;
431
432 while(start < end) {
433 cache64_unroll32(start,Hit_Writeback_Inv_SD);
434 start += 0x800;
435 }
436 }
437
438 extern inline void blast_scache64_page_indexed(unsigned long page)
439 {
440 unsigned long start = page;
441 unsigned long end = page + PAGE_SIZE;
442
443 while(start < end) {
444 cache64_unroll32(start,Index_Writeback_Inv_SD);
445 start += 0x800;
446 }
447 }
448
449 #define cache128_unroll32(base,op) \
450 __asm__ __volatile__(" \
451 .set noreorder; \
452 cache %1, 0x000(%0); cache %1, 0x080(%0); \
453 cache %1, 0x100(%0); cache %1, 0x180(%0); \
454 cache %1, 0x200(%0); cache %1, 0x280(%0); \
455 cache %1, 0x300(%0); cache %1, 0x380(%0); \
456 cache %1, 0x400(%0); cache %1, 0x480(%0); \
457 cache %1, 0x500(%0); cache %1, 0x580(%0); \
458 cache %1, 0x600(%0); cache %1, 0x680(%0); \
459 cache %1, 0x700(%0); cache %1, 0x780(%0); \
460 cache %1, 0x800(%0); cache %1, 0x880(%0); \
461 cache %1, 0x900(%0); cache %1, 0x980(%0); \
462 cache %1, 0xa00(%0); cache %1, 0xa80(%0); \
463 cache %1, 0xb00(%0); cache %1, 0xb80(%0); \
464 cache %1, 0xc00(%0); cache %1, 0xc80(%0); \
465 cache %1, 0xd00(%0); cache %1, 0xd80(%0); \
466 cache %1, 0xe00(%0); cache %1, 0xe80(%0); \
467 cache %1, 0xf00(%0); cache %1, 0xf80(%0); \
468 .set reorder" \
469 : \
470 : "r" (base), \
471 "i" (op));
472
473 extern inline void blast_scache128(void)
474 {
475 unsigned long start = KSEG0;
476 unsigned long end = KSEG0 + scache_size;
477
478 while(start < end) {
479 cache128_unroll32(start,Index_Writeback_Inv_SD);
480 start += 0x1000;
481 }
482 }
483
484 extern inline void blast_scache128_page(unsigned long page)
485 {
486 cache128_unroll32(page,Hit_Writeback_Inv_SD);
487 }
488
489 extern inline void blast_scache128_page_indexed(unsigned long page)
490 {
491 cache128_unroll32(page,Index_Writeback_Inv_SD);
492 }
493
494 #endif /* __ASM_R4KCACHE_H */
495
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