1 /*
2 * include/asm-parisc/cache.h
3 */
4
5 #ifndef __ARCH_PARISC_CACHE_H
6 #define __ARCH_PARISC_CACHE_H
7
8 /*
9 ** XXX FIXME : L1_CACHE_BYTES (cacheline size) should be a boot time thing.
10 **
11 ** 32-bit on PA2.0 is not covered well by the #ifdef __LP64__ below.
12 ** PA2.0 processors have 64-byte cachelines.
13 **
14 ** The issue is mostly cacheline ping-ponging on SMP boxes.
15 ** To avoid this, code should define stuff to be per CPU on cacheline
16 ** aligned boundaries. This can make a 2x or more difference in perf
17 ** depending on how badly the thrashing is.
18 **
19 ** We don't need to worry about I/O since all PA2.0 boxes (except T600)
20 ** are I/O coherent. That means flushing less than you needed to generally
21 ** doesn't matter - the I/O MMU will read/modify/write the cacheline.
22 **
23 ** (Digression: it is possible to program I/O MMU's to not first read
24 ** a cacheline for inbound data - ie just grab ownership and start writing.
25 ** While it improves I/O throughput, you gotta know the device driver
26 ** is well behaved and can deal with the issues.)
27 */
28 #if defined(__LP64__)
29 #define L1_CACHE_BYTES 64
30 #else
31 #define L1_CACHE_BYTES 32
32 #endif
33
34 #define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
35
36 #define SMP_CACHE_BYTES L1_CACHE_BYTES
37
38 #define __cacheline_aligned __attribute__((__aligned__(L1_CACHE_BYTES)))
39
40 extern void init_cache(void); /* initializes cache-flushing */
41 extern void flush_data_cache(void); /* flushes data-cache only */
42 extern void flush_instruction_cache(void);/* flushes code-cache only */
43 extern void flush_all_caches(void); /* flushes code and data-cache */
44
45 extern int get_cache_info(char *);
46
47 extern struct pdc_cache_info cache_info;
48
49 #define fdce(addr) asm volatile("fdce 0(%0)" : : "r" (addr))
50 #define fice(addr) asm volatile("fice 0(%%sr1,%0)" : : "r" (addr))
51
52 #define pdtlbe(addr) asm volatile("pdtlbe 0(%%sr1,%0)" : : "r" (addr))
53 #define pdtlb_kernel(addr) asm volatile("pdtlb 0(%0)" : : "r" (addr));
54 #define pitlbe(addr) asm volatile("pitlbe 0(%%sr1,%0)" : : "r" (addr))
55
56 #define kernel_fdc(addr) asm volatile("fdc 0(%%sr0, %0)" : : "r" (addr))
57
58 #endif
59
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