1 /*
2 * parisc mmu structures
3 */
4
5 #ifndef _PARISC_MMU_H_
6 #define _PARISC_MMU_H_
7
8 #ifndef __ASSEMBLY__
9
10 /* Default "unsigned long" context */
11 typedef unsigned long mm_context_t;
12
13 /* Hardware Page Table Entry */
14 typedef struct _PTE {
15 unsigned long v:1; /* Entry is valid */
16 unsigned long tag:31; /* Unique Tag */
17
18 unsigned long r:1; /* referenced */
19 unsigned long os_1:1; /* */
20 unsigned long t:1; /* page reference trap */
21 unsigned long d:1; /* dirty */
22 unsigned long b:1; /* break */
23 unsigned long type:3; /* access type */
24 unsigned long pl1:2; /* PL1 (execute) */
25 unsigned long pl2:2; /* PL2 (write) */
26 unsigned long u:1; /* uncacheable */
27 unsigned long id:1; /* access id */
28 unsigned long os_2:1; /* */
29
30 unsigned long os_3:3; /* */
31 unsigned long res_1:4; /* */
32 unsigned long phys:20; /* physical page number */
33 unsigned long os_4:2; /* */
34 unsigned long res_2:3; /* */
35
36 unsigned long next; /* pointer to next page */
37 } PTE;
38
39 /*
40 * Simulated two-level MMU. This structure is used by the kernel
41 * to keep track of MMU mappings and is used to update/maintain
42 * the hardware HASH table which is really a cache of mappings.
43 *
44 * The simulated structures mimic the hardware available on other
45 * platforms, notably the 80x86 and 680x0.
46 */
47
48 typedef struct _pte {
49 unsigned long page_num:20;
50 unsigned long flags:12; /* Page flags (some unused bits) */
51 } pte;
52
53 #define PD_SHIFT (10+12) /* Page directory */
54 #define PD_MASK 0x02FF
55 #define PT_SHIFT (12) /* Page Table */
56 #define PT_MASK 0x02FF
57 #define PG_SHIFT (12) /* Page Entry */
58
59 /* MMU context */
60
61 typedef struct _MMU_context {
62 long pid[4];
63 pte **pmap; /* Two-level page-map structure */
64 } MMU_context;
65
66 #endif /* __ASSEMBLY__ */
67
68 #endif /* _PARISC_MMU_H_ */
69
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