1 #ifndef __PARISC_SYSTEM_H
2 #define __PARISC_SYSTEM_H
3
4 #include <linux/config.h>
5 #include <asm/psw.h>
6
7 /* The program status word as bitfields. */
8 struct pa_psw {
9 unsigned int y:1;
10 unsigned int z:1;
11 unsigned int rv:2;
12 unsigned int w:1;
13 unsigned int e:1;
14 unsigned int s:1;
15 unsigned int t:1;
16
17 unsigned int h:1;
18 unsigned int l:1;
19 unsigned int n:1;
20 unsigned int x:1;
21 unsigned int b:1;
22 unsigned int c:1;
23 unsigned int v:1;
24 unsigned int m:1;
25
26 unsigned int cb:8;
27
28 unsigned int o:1;
29 unsigned int g:1;
30 unsigned int f:1;
31 unsigned int r:1;
32 unsigned int q:1;
33 unsigned int p:1;
34 unsigned int d:1;
35 unsigned int i:1;
36 };
37
38 #define pa_psw(task) ((struct pa_psw *) ((char *) (task) + TASK_PT_PSW))
39
40 struct task_struct;
41
42 extern struct task_struct *_switch_to(struct task_struct *, struct task_struct *);
43
44 #define prepare_to_switch() do { } while(0)
45 #define switch_to(prev, next, last) do { \
46 (last) = _switch_to(prev, next); \
47 } while(0)
48
49 /* borrowed this from sparc64 -- probably the SMP case is hosed for us */
50 #ifdef CONFIG_SMP
51 #define smp_mb() mb()
52 #define smp_rmb() rmb()
53 #define smp_wmb() wmb()
54 #else
55 /* This is simply the barrier() macro from linux/kernel.h but when serial.c
56 * uses tqueue.h uses smp_mb() defined using barrier(), linux/kernel.h
57 * hasn't yet been included yet so it fails, thus repeating the macro here.
58 */
59 #define smp_mb() __asm__ __volatile__("":::"memory");
60 #define smp_rmb() __asm__ __volatile__("":::"memory");
61 #define smp_wmb() __asm__ __volatile__("":::"memory");
62 #endif
63
64 /* interrupt control */
65 #define __save_flags(x) __asm__ __volatile__("ssm 0, %0" : "=r" (x) : : "memory")
66 #define __restore_flags(x) __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory")
67 #define __cli() __asm__ __volatile__("rsm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
68 #define __sti() __asm__ __volatile__("ssm %0,%%r0\n" : : "i" (PSW_I) : "memory" )
69
70 #define local_irq_save(x) \
71 __asm__ __volatile__("rsm %1,%0" : "=r" (x) :"i" (PSW_I) : "memory" )
72 #define local_irq_restore(x) \
73 __asm__ __volatile__("mtsm %0" : : "r" (x) : "memory" )
74 #define local_irq_disable() __cli()
75 #define local_irq_enable() __sti()
76
77 #ifdef CONFIG_SMP
78 #else
79 #define cli() __cli()
80 #define sti() __sti()
81 #define save_flags(x) __save_flags(x)
82 #define restore_flags(x) __restore_flags(x)
83 #endif
84
85
86 #define mfctl(reg) ({ \
87 unsigned long cr; \
88 __asm__ __volatile__( \
89 "mfctl " #reg ",%0" : \
90 "=r" (cr) \
91 ); \
92 cr; \
93 })
94
95 #define mtctl(gr, cr) \
96 __asm__ __volatile__("mtctl %0,%1" \
97 : /* no outputs */ \
98 : "r" (gr), "i" (cr))
99
100 /* these are here to de-mystefy the calling code, and to provide hooks */
101 /* which I needed for debugging EIEM problems -PB */
102 #define get_eiem() mfctl(15)
103 static inline void set_eiem(unsigned long val)
104 {
105 mtctl(val, 15);
106 }
107
108 #define mfsp(reg) ({ \
109 unsigned long cr; \
110 __asm__ __volatile__( \
111 "mfsp " #reg ",%0" : \
112 "=r" (cr) \
113 ); \
114 cr; \
115 })
116
117 #define mtsp(gr, cr) \
118 __asm__ __volatile__("mtsp %0,%1" \
119 : /* no outputs */ \
120 : "r" (gr), "i" (cr))
121
122
123 #define mb() __asm__ __volatile__ ("sync" : : :"memory")
124 #define wmb() mb()
125
126 extern unsigned long __xchg(unsigned long, unsigned long *, int);
127
128 #define xchg(ptr,x) \
129 (__typeof__(*(ptr)))__xchg((unsigned long)(x),(unsigned long*)(ptr),sizeof(*(ptr)))
130
131 /* LDCW, the only atomic read-write operation PA-RISC has. Sigh. */
132 #define __ldcw(a) ({ \
133 unsigned __ret; \
134 __asm__ __volatile__("ldcw 0(%1),%0" : "=r" (__ret) : "r" (a)); \
135 __ret; \
136 })
137
138 #ifdef CONFIG_SMP
139 /*
140 * Your basic SMP spinlocks, allowing only a single CPU anywhere
141 */
142
143 typedef struct {
144 volatile unsigned int __attribute__((aligned(16))) lock;
145 } spinlock_t;
146 #endif
147
148 #endif
149
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