1
2 /*
3 * MPC8xx Internal Memory Map
4 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 *
6 * The I/O on the MPC860 is comprised of blocks of special registers
7 * and the dual port ram for the Communication Processor Module.
8 * Within this space are functional units such as the SIU, memory
9 * controller, system timers, and other control functions. It is
10 * a combination that I found difficult to separate into logical
11 * functional files.....but anyone else is welcome to try. -- Dan
12 */
13 #ifdef __KERNEL__
14 #ifndef __IMMAP_8XX__
15 #define __IMMAP_8XX__
16
17 /* System configuration registers.
18 */
19 typedef struct sys_conf {
20 uint sc_siumcr;
21 uint sc_sypcr;
22 uint sc_swt;
23 char res1[2];
24 ushort sc_swsr;
25 uint sc_sipend;
26 uint sc_simask;
27 uint sc_siel;
28 uint sc_sivec;
29 uint sc_tesr;
30 char res2[0xc];
31 uint sc_sdcr;
32 char res3[0x4c];
33 } sysconf8xx_t;
34
35 /* PCMCIA configuration registers.
36 */
37 typedef struct pcmcia_conf {
38 uint pcmc_pbr0;
39 uint pcmc_por0;
40 uint pcmc_pbr1;
41 uint pcmc_por1;
42 uint pcmc_pbr2;
43 uint pcmc_por2;
44 uint pcmc_pbr3;
45 uint pcmc_por3;
46 uint pcmc_pbr4;
47 uint pcmc_por4;
48 uint pcmc_pbr5;
49 uint pcmc_por5;
50 uint pcmc_pbr6;
51 uint pcmc_por6;
52 uint pcmc_pbr7;
53 uint pcmc_por7;
54 char res1[0x20];
55 uint pcmc_pgcra;
56 uint pcmc_pgcrb;
57 uint pcmc_pscr;
58 char res2[4];
59 uint pcmc_pipr;
60 char res3[4];
61 uint pcmc_per;
62 char res4[4];
63 } pcmconf8xx_t;
64
65 /* Memory controller registers.
66 */
67 typedef struct mem_ctlr {
68 uint memc_br0;
69 uint memc_or0;
70 uint memc_br1;
71 uint memc_or1;
72 uint memc_br2;
73 uint memc_or2;
74 uint memc_br3;
75 uint memc_or3;
76 uint memc_br4;
77 uint memc_or4;
78 uint memc_br5;
79 uint memc_or5;
80 uint memc_br6;
81 uint memc_or6;
82 uint memc_br7;
83 uint memc_or7;
84 char res1[0x24];
85 uint memc_mar;
86 uint memc_mcr;
87 char res2[4];
88 uint memc_mamr;
89 uint memc_mbmr;
90 ushort memc_mstat;
91 ushort memc_mptpr;
92 uint memc_mdr;
93 char res3[0x80];
94 } memctl8xx_t;
95
96 /* System Integration Timers.
97 */
98 typedef struct sys_int_timers {
99 ushort sit_tbscr;
100 uint sit_tbreff0;
101 uint sit_tbreff1;
102 char res1[0x14];
103 ushort sit_rtcsc;
104 uint sit_rtc;
105 uint sit_rtsec;
106 uint sit_rtcal;
107 char res2[0x10];
108 ushort sit_piscr;
109 char res3[2];
110 uint sit_pitc;
111 uint sit_pitr;
112 char res4[0x34];
113 } sit8xx_t;
114
115 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
116 #define TBSCR_REFA ((ushort)0x0080)
117 #define TBSCR_REFB ((ushort)0x0040)
118 #define TBSCR_REFAE ((ushort)0x0008)
119 #define TBSCR_REFBE ((ushort)0x0004)
120 #define TBSCR_TBF ((ushort)0x0002)
121 #define TBSCR_TBE ((ushort)0x0001)
122
123 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
124 #define RTCSC_SEC ((ushort)0x0080)
125 #define RTCSC_ALR ((ushort)0x0040)
126 #define RTCSC_38K ((ushort)0x0010)
127 #define RTCSC_SIE ((ushort)0x0008)
128 #define RTCSC_ALE ((ushort)0x0004)
129 #define RTCSC_RTF ((ushort)0x0002)
130 #define RTCSC_RTE ((ushort)0x0001)
131
132 #define PISCR_PIRQ_MASK ((ushort)0xff00)
133 #define PISCR_PS ((ushort)0x0080)
134 #define PISCR_PIE ((ushort)0x0004)
135 #define PISCR_PTF ((ushort)0x0002)
136 #define PISCR_PTE ((ushort)0x0001)
137
138 /* Clocks and Reset.
139 */
140 typedef struct clk_and_reset {
141 uint car_sccr;
142 uint car_plprcr;
143 uint car_rsr;
144 char res[0x74]; /* Reserved area */
145 } car8xx_t;
146
147 /* System Integration Timers keys.
148 */
149 typedef struct sitk {
150 uint sitk_tbscrk;
151 uint sitk_tbreff0k;
152 uint sitk_tbreff1k;
153 uint sitk_tbk;
154 char res1[0x10];
155 uint sitk_rtcsck;
156 uint sitk_rtck;
157 uint sitk_rtseck;
158 uint sitk_rtcalk;
159 char res2[0x10];
160 uint sitk_piscrk;
161 uint sitk_pitck;
162 char res3[0x38];
163 } sitk8xx_t;
164
165 /* Clocks and reset keys.
166 */
167 typedef struct cark {
168 uint cark_sccrk;
169 uint cark_plprcrk;
170 uint cark_rsrk;
171 char res[0x474];
172 } cark8xx_t;
173
174 /* The key to unlock registers maintained by keep-alive power.
175 */
176 #define KAPWR_KEY ((unsigned int)0x55ccaa33)
177
178 /* LCD interface. MPC821 Only.
179 */
180 typedef struct lcd {
181 ushort lcd_lcolr[16];
182 char res[0x20];
183 uint lcd_lccr;
184 uint lcd_lchcr;
185 uint lcd_lcvcr;
186 char res2[4];
187 uint lcd_lcfaa;
188 uint lcd_lcfba;
189 char lcd_lcsr;
190 char res3[0x7];
191 } lcd8xx_t;
192
193 /* I2C
194 */
195 typedef struct i2c {
196 u_char i2c_i2mod;
197 char res1[3];
198 u_char i2c_i2add;
199 char res2[3];
200 u_char i2c_i2brg;
201 char res3[3];
202 u_char i2c_i2com;
203 char res4[3];
204 u_char i2c_i2cer;
205 char res5[3];
206 u_char i2c_i2cmr;
207 char res6[0x8b];
208 } i2c8xx_t;
209
210 /* DMA control/status registers.
211 */
212 typedef struct sdma_csr {
213 char res1[4];
214 uint sdma_sdar;
215 u_char sdma_sdsr;
216 char res3[3];
217 u_char sdma_sdmr;
218 char res4[3];
219 u_char sdma_idsr1;
220 char res5[3];
221 u_char sdma_idmr1;
222 char res6[3];
223 u_char sdma_idsr2;
224 char res7[3];
225 u_char sdma_idmr2;
226 char res8[0x13];
227 } sdma8xx_t;
228
229 /* Communication Processor Module Interrupt Controller.
230 */
231 typedef struct cpm_ic {
232 ushort cpic_civr;
233 char res[0xe];
234 uint cpic_cicr;
235 uint cpic_cipr;
236 uint cpic_cimr;
237 uint cpic_cisr;
238 } cpic8xx_t;
239
240 /* Input/Output Port control/status registers.
241 */
242 typedef struct io_port {
243 ushort iop_padir;
244 ushort iop_papar;
245 ushort iop_paodr;
246 ushort iop_padat;
247 char res1[8];
248 ushort iop_pcdir;
249 ushort iop_pcpar;
250 ushort iop_pcso;
251 ushort iop_pcdat;
252 ushort iop_pcint;
253 char res2[6];
254 ushort iop_pddir;
255 ushort iop_pdpar;
256 char res3[2];
257 ushort iop_pddat;
258 char res4[8];
259 } iop8xx_t;
260
261 /* Communication Processor Module Timers
262 */
263 typedef struct cpm_timers {
264 ushort cpmt_tgcr;
265 char res1[0xe];
266 ushort cpmt_tmr1;
267 ushort cpmt_tmr2;
268 ushort cpmt_trr1;
269 ushort cpmt_trr2;
270 ushort cpmt_tcr1;
271 ushort cpmt_tcr2;
272 ushort cpmt_tcn1;
273 ushort cpmt_tcn2;
274 ushort cpmt_tmr3;
275 ushort cpmt_tmr4;
276 ushort cpmt_trr3;
277 ushort cpmt_trr4;
278 ushort cpmt_tcr3;
279 ushort cpmt_tcr4;
280 ushort cpmt_tcn3;
281 ushort cpmt_tcn4;
282 ushort cpmt_ter1;
283 ushort cpmt_ter2;
284 ushort cpmt_ter3;
285 ushort cpmt_ter4;
286 char res2[8];
287 } cpmtimer8xx_t;
288
289 /* Finally, the Communication Processor stuff.....
290 */
291 typedef struct scc { /* Serial communication channels */
292 uint scc_gsmrl;
293 uint scc_gsmrh;
294 ushort scc_pmsr;
295 char res1[2];
296 ushort scc_todr;
297 ushort scc_dsr;
298 ushort scc_scce;
299 char res2[2];
300 ushort scc_sccm;
301 char res3;
302 u_char scc_sccs;
303 char res4[8];
304 } scc_t;
305
306 typedef struct smc { /* Serial management channels */
307 char res1[2];
308 ushort smc_smcmr;
309 char res2[2];
310 u_char smc_smce;
311 char res3[3];
312 u_char smc_smcm;
313 char res4[5];
314 } smc_t;
315
316 /* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
317 * it fits within the address space.
318 */
319 typedef struct fec {
320 uint fec_addr_low; /* LS 32 bits of station address */
321 ushort fec_addr_high; /* MS 16 bits of address */
322 ushort res1;
323 uint fec_hash_table_high;
324 uint fec_hash_table_low;
325 uint fec_r_des_start;
326 uint fec_x_des_start;
327 uint fec_r_buff_size;
328 uint res2[9];
329 uint fec_ecntrl;
330 uint fec_ievent;
331 uint fec_imask;
332 uint fec_ivec;
333 uint fec_r_des_active;
334 uint fec_x_des_active;
335 uint res3[10];
336 uint fec_mii_data;
337 uint fec_mii_speed;
338 uint res4[17];
339 uint fec_r_bound;
340 uint fec_r_fstart;
341 uint res5[6];
342 uint fec_x_fstart;
343 uint res6[17];
344 uint fec_fun_code;
345 uint res7[3];
346 uint fec_r_cntrl;
347 uint fec_r_hash;
348 uint res8[14];
349 uint fec_x_cntrl;
350 uint res9[0x1e];
351 } fec_t;
352
353 typedef struct comm_proc {
354 /* General control and status registers.
355 */
356 ushort cp_cpcr;
357 char res1[2];
358 ushort cp_rccr;
359 char res2[6];
360 ushort cp_cpmcr1;
361 ushort cp_cpmcr2;
362 ushort cp_cpmcr3;
363 ushort cp_cpmcr4;
364 char res3[2];
365 ushort cp_rter;
366 char res4[2];
367 ushort cp_rtmr;
368 char res5[0x14];
369
370 /* Baud rate generators.
371 */
372 uint cp_brgc1;
373 uint cp_brgc2;
374 uint cp_brgc3;
375 uint cp_brgc4;
376
377 /* Serial Communication Channels.
378 */
379 scc_t cp_scc[4];
380
381 /* Serial Management Channels.
382 */
383 smc_t cp_smc[2];
384
385 /* Serial Peripheral Interface.
386 */
387 ushort cp_spmode;
388 char res6[4];
389 u_char cp_spie;
390 char res7[3];
391 u_char cp_spim;
392 char res8[2];
393 u_char cp_spcom;
394 char res9[2];
395
396 /* Parallel Interface Port.
397 */
398 char res10[2];
399 ushort cp_pipc;
400 char res11[2];
401 ushort cp_ptpr;
402 uint cp_pbdir;
403 uint cp_pbpar;
404 char res12[2];
405 ushort cp_pbodr;
406 uint cp_pbdat;
407 char res13[0x18];
408
409 /* Serial Interface and Time Slot Assignment.
410 */
411 uint cp_simode;
412 u_char cp_sigmr;
413 char res14;
414 u_char cp_sistr;
415 u_char cp_sicmr;
416 char res15[4];
417 uint cp_sicr;
418 uint cp_sirp;
419 char res16[0x10c];
420 u_char cp_siram[0x200];
421
422 /* The fast ethernet controller is not really part of the CPM,
423 * but it resides in the address space.
424 */
425 fec_t cp_fec;
426 char res18[0x1000];
427
428 /* Dual Ported RAM follows.
429 * There are many different formats for this memory area
430 * depending upon the devices used and options chosen.
431 */
432 u_char cp_dpmem[0x1000]; /* BD / Data / ucode */
433 u_char res19[0xc00];
434 u_char cp_dparam[0x400]; /* Parameter RAM */
435 } cpm8xx_t;
436
437 /* Internal memory map.
438 */
439 typedef struct immap {
440 sysconf8xx_t im_siu_conf; /* SIU Configuration */
441 pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
442 memctl8xx_t im_memctl; /* Memory Controller */
443 sit8xx_t im_sit; /* System integration timers */
444 car8xx_t im_clkrst; /* Clocks and reset */
445 sitk8xx_t im_sitk; /* Sys int timer keys */
446 cark8xx_t im_clkrstk; /* Clocks and reset keys */
447 lcd8xx_t im_lcd; /* LCD (821 only) */
448 i2c8xx_t im_i2c; /* I2C control/status */
449 sdma8xx_t im_sdma; /* SDMA control/status */
450 cpic8xx_t im_cpic; /* CPM Interrupt Controller */
451 iop8xx_t im_ioport; /* IO Port control/status */
452 cpmtimer8xx_t im_cpmtimer; /* CPM timers */
453 cpm8xx_t im_cpm; /* Communication processor */
454 } immap_t;
455
456 #endif /* __IMMAP_8XX__ */
457 #endif /* __KERNEL__ */
458
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