~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~ [ freetext search ] ~ [ file search ] ~

Linux Cross Reference
Linux/include/asm-ppc/heathrow.h

Version: ~ [ 2.4.0 ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 /*
  2  * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
  3  *
  4  * Grabbed from Open Firmware definitions on a PowerBook G3 Series
  5  *
  6  * Copyright (C) 1997 Paul Mackerras.
  7  */
  8 
  9 /* offset from ohare base for feature control register */
 10 #define HEATHROW_FEATURE_REG    0x38
 11 
 12 /*
 13  * Bits in feature control register.
 14  * Bits postfixed with a _N are in inverse logic
 15  */
 16 #define HRW_RESET_SCC           0x00000001      /* Named in_use_led in OF ??? */
 17 #define HRW_BAY_POWER_N         0x00000002
 18 #define HRW_BAY_PCI_ENABLE      0x00000004
 19 #define HRW_BAY_IDE_ENABLE      0x00000008
 20 #define HRW_BAY_FLOPPY_ENABLE   0x00000010
 21 #define HRW_IDE0_ENABLE         0x00000020
 22 #define HRW_IDE0_RESET_N        0x00000040
 23 #define HRW_BAY_RESET_N         0x00000080
 24 #define HRW_IOBUS_ENABLE        0x00000100      /* Internal IDE ? */
 25 #define HRW_SCC_ENABLE          0x00000200
 26 #define HRW_MESH_ENABLE         0x00000400
 27 #define HRW_SWIM_ENABLE         0x00000800
 28 #define HRW_SOUND_POWER_N       0x00001000
 29 #define HRW_SOUND_CLK_ENABLE    0x00002000
 30 #define HRW_SCCA_IO             0x00004000
 31 #define HRW_SCCB_IO             0x00008000
 32 #define HRW_PORT_OR_DESK_VIA_N  0x00010000      /* This one is 0 on PowerBook */
 33 #define HRW_PWM_MON_ID_N        0x00020000      /* ??? (0) */
 34 #define HRW_HOOK_MB_CNT_N       0x00040000      /* ??? (0) */
 35 #define HRW_SWIM_CLONE_FLOPPY   0x00080000      /* ??? (0) */
 36 #define HRW_AUD_RUN22           0x00100000      /* ??? (1) */
 37 #define HRW_SCSI_LINK_MODE      0x00200000      /* Read ??? (1) */
 38 #define HRW_ARB_BYPASS          0x00400000      /* ??? (0 on main, 1 on gatwick) */
 39 #define HRW_IDE1_RESET_N        0x00800000      /* Media bay */
 40 #define HRW_SLOW_SCC_PCLK       0x01000000      /* ??? (0) */
 41 #define HRW_MODEM_POWER_N       0x02000000      /* Used by internal modem on wallstreet */
 42 #define HRW_MFDC_CELL_ENABLE    0x04000000      /* ??? (0) */
 43 #define HRW_USE_MFDC            0x08000000      /* ??? (0) */
 44 #define HRW_BMAC_IO_ENABLE      0x60000000      /* two bits, not documented in OF */
 45 #define HRW_BMAC_RESET          0x80000000      /* not documented in OF */
 46 
 47 /* We OR those features at boot on desktop G3s */
 48 #define HRW_DEFAULTS            (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
 49 
 50 /* Those seem to be different on paddington */
 51 #define PADD_MODEM_POWER_N      0x00000001      /* modem power on paddington */
 52 #define PADD_RESET_SCC          0x02000000      /* check this please */
 53 

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~ [ freetext search ] ~ [ file search ] ~

This page was automatically generated by the LXR engine.
Visit the LXR main site for more information.