1
2 /*
3 * MPC8260 Internal Memory Map
4 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
5 *
6 * The Internal Memory Map of the 8260. I don't know how generic
7 * this will be, as I don't have any knowledge of the subsequent
8 * parts at this time. I copied this from the 8xx_immap.h.
9 */
10 #ifdef __KERNEL__
11 #ifndef __IMMAP_82XX__
12 #define __IMMAP_82XX__
13
14 /* System configuration registers.
15 */
16 typedef struct sys_conf {
17 uint sc_siumcr;
18 uint sc_sypcr;
19 char res1[6];
20 ushort sc_swsr;
21 char res2[20];
22 uint sc_bcr;
23 u_char sc_ppc_acr;
24 char res3[3];
25 uint sc_ppc_alrh;
26 uint sc_ppc_alrl;
27 u_char sc_lcl_acr;
28 char res4[3];
29 uint sc_lcl_alrh;
30 uint sc_lcl_alrl;
31 uint sc_tescr1;
32 uint sc_tescr2;
33 uint sc_ltescr1;
34 uint sc_ltescr2;
35 uint sc_pdtea;
36 u_char sc_pdtem;
37 char res5[3];
38 uint sc_ldtea;
39 u_char sc_ldtem;
40 char res6[163];
41 } sysconf8260_t;
42
43
44 /* Memory controller registers.
45 */
46 typedef struct mem_ctlr {
47 uint memc_br0;
48 uint memc_or0;
49 uint memc_br1;
50 uint memc_or1;
51 uint memc_br2;
52 uint memc_or2;
53 uint memc_br3;
54 uint memc_or3;
55 uint memc_br4;
56 uint memc_or4;
57 uint memc_br5;
58 uint memc_or5;
59 uint memc_br6;
60 uint memc_or6;
61 uint memc_br7;
62 uint memc_or7;
63 uint memc_br8;
64 uint memc_or8;
65 uint memc_br9;
66 uint memc_or9;
67 uint memc_br10;
68 uint memc_or10;
69 uint memc_br11;
70 uint memc_or11;
71 char res1[8];
72 uint memc_mar;
73 char res2[4];
74 uint memc_mamr;
75 uint memc_mbmr;
76 uint memc_mcmr;
77 char res3[8];
78 ushort memc_mptpr;
79 char res4[2];
80 uint memc_mdr;
81 char res5[4];
82 uint memc_psdmr;
83 uint memc_lsdmr;
84 u_char memc_purt;
85 char res6[3];
86 u_char memc_psrt;
87 char res7[3];
88 u_char memc_lurt;
89 char res8[3];
90 u_char memc_lsrt;
91 char res9[3];
92 uint memc_immr;
93 char res10[84];
94 } memctl8260_t;
95
96 /* System Integration Timers.
97 */
98 typedef struct sys_int_timers {
99 char res1[32];
100 ushort sit_tmcntsc;
101 char res2[2];
102 uint sit_tmcnt;
103 char res3[4];
104 uint sit_tmcntal;
105 char res4[16];
106 ushort sit_piscr;
107 char res5[2];
108 uint sit_pitc;
109 uint sit_pitr;
110 char res6[94];
111 char res7[2390];
112 } sit8260_t;
113
114 #define PISCR_PIRQ_MASK ((ushort)0xff00)
115 #define PISCR_PS ((ushort)0x0080)
116 #define PISCR_PIE ((ushort)0x0004)
117 #define PISCR_PTF ((ushort)0x0002)
118 #define PISCR_PTE ((ushort)0x0001)
119
120 /* Interrupt Controller.
121 */
122 typedef struct interrupt_controller {
123 ushort ic_sicr;
124 char res1[2];
125 uint ic_sivec;
126 uint ic_sipnrh;
127 uint ic_sipnrl;
128 uint ic_siprr;
129 uint ic_scprrh;
130 uint ic_scprrl;
131 uint ic_simrh;
132 uint ic_simrl;
133 uint ic_siexr;
134 char res2[88];
135 } intctl8260_t;
136
137 /* Clocks and Reset.
138 */
139 typedef struct clk_and_reset {
140 uint car_sccr;
141 char res1[4];
142 uint car_scmr;
143 char res2[4];
144 uint car_rsr;
145 uint car_rmr;
146 char res[104];
147 } car8260_t;
148
149 /* Input/Output Port control/status registers.
150 * Names consistent with processor manual, although they are different
151 * from the original 8xx names.......
152 */
153 typedef struct io_port {
154 uint iop_pdira;
155 uint iop_ppara;
156 uint iop_psora;
157 uint iop_podra;
158 uint iop_pdata;
159 char res1[12];
160 uint iop_pdirb;
161 uint iop_pparb;
162 uint iop_psorb;
163 uint iop_podrb;
164 uint iop_pdatb;
165 char res2[12];
166 uint iop_pdirc;
167 uint iop_pparc;
168 uint iop_psorc;
169 uint iop_podrc;
170 uint iop_pdatc;
171 char res3[12];
172 uint iop_pdird;
173 uint iop_ppard;
174 uint iop_psord;
175 uint iop_podrd;
176 uint iop_pdatd;
177 char res4[12];
178 } iop8260_t;
179
180 /* Communication Processor Module Timers
181 */
182 typedef struct cpm_timers {
183 u_char cpmt_tgcr1;
184 char res1[3];
185 u_char cpmt_tgcr2;
186 char res2[11];
187 ushort cpmt_tmr1;
188 ushort cpmt_tmr2;
189 ushort cpmt_trr1;
190 ushort cpmt_trr2;
191 ushort cpmt_tcr1;
192 ushort cpmt_tcr2;
193 ushort cpmt_tcn1;
194 ushort cpmt_tcn2;
195 ushort cpmt_tmr3;
196 ushort cpmt_tmr4;
197 ushort cpmt_trr3;
198 ushort cpmt_trr4;
199 ushort cpmt_tcr3;
200 ushort cpmt_tcr4;
201 ushort cpmt_tcn3;
202 ushort cpmt_tcn4;
203 ushort cpmt_ter1;
204 ushort cpmt_ter2;
205 ushort cpmt_ter3;
206 ushort cpmt_ter4;
207 char res3[584];
208 } cpmtimer8260_t;
209
210 /* DMA control/status registers.
211 */
212 typedef struct sdma_csr {
213 char res0[24];
214 u_char sdma_sdsr;
215 char res1[3];
216 u_char sdma_sdmr;
217 char res2[3];
218 u_char sdma_idsr1;
219 char res3[3];
220 u_char sdma_idmr1;
221 char res4[3];
222 u_char sdma_idsr2;
223 char res5[3];
224 u_char sdma_idmr2;
225 char res6[3];
226 u_char sdma_idsr3;
227 char res7[3];
228 u_char sdma_idmr3;
229 char res8[3];
230 u_char sdma_idsr4;
231 char res9[3];
232 u_char sdma_idmr4;
233 char res10[707];
234 } sdma8260_t;
235
236 /* Fast controllers
237 */
238 typedef struct fcc {
239 uint fcc_gfmr;
240 uint fcc_fpsmr;
241 ushort fcc_ftodr;
242 char res1[2];
243 ushort fcc_fdsr;
244 char res2[2];
245 ushort fcc_fcce;
246 char res3[2];
247 ushort fcc_fccm;
248 char res4[2];
249 u_char fcc_fccs;
250 char res5[3];
251 u_char fcc_ftirr_phy[4];
252 } fcc_t;
253
254 /* I2C
255 */
256 typedef struct i2c {
257 u_char i2c_i2mod;
258 char res1[3];
259 u_char i2c_i2add;
260 char res2[3];
261 u_char i2c_i2brg;
262 char res3[3];
263 u_char i2c_i2com;
264 char res4[3];
265 u_char i2c_i2cer;
266 char res5[3];
267 u_char i2c_i2cmr;
268 char res6[331];
269 } i2c8260_t;
270
271 typedef struct scc { /* Serial communication channels */
272 uint scc_gsmrl;
273 uint scc_gsmrh;
274 ushort scc_pmsr;
275 char res1[2];
276 ushort scc_todr;
277 ushort scc_dsr;
278 ushort scc_scce;
279 char res2[2];
280 ushort scc_sccm;
281 char res3;
282 u_char scc_sccs;
283 char res4[8];
284 } scc_t;
285
286 typedef struct smc { /* Serial management channels */
287 char res1[2];
288 ushort smc_smcmr;
289 char res2[2];
290 u_char smc_smce;
291 char res3[3];
292 u_char smc_smcm;
293 char res4[5];
294 } smc_t;
295
296 /* Serial Peripheral Interface.
297 */
298 typedef struct spi {
299 ushort spi_spmode;
300 char res1[4];
301 u_char spi_spie;
302 char res2[3];
303 u_char spi_spim;
304 char res3[2];
305 u_char spi_spcom;
306 char res4[82];
307 } spi_t;
308
309 /* CPM Mux.
310 */
311 typedef struct cpmux {
312 u_char cmx_si1cr;
313 char res1;
314 u_char cmx_si2cr;
315 char res2;
316 uint cmx_fcr;
317 uint cmx_scr;
318 u_char cmx_smr;
319 char res3;
320 ushort cmx_uar;
321 char res4[16];
322 } cpmux_t;
323
324 /* SIRAM control
325 */
326 typedef struct siram {
327 ushort si_amr;
328 ushort si_bmr;
329 ushort si_cmr;
330 ushort si_dmr;
331 u_char si_gmr;
332 char res1;
333 u_char si_cmdr;
334 char res2;
335 u_char si_str;
336 char res3;
337 ushort si_rsr;
338 } siramctl_t;
339
340 typedef struct mcc {
341 ushort mcc_mcce;
342 char res1[2];
343 ushort mcc_mccm;
344 char res2[2];
345 u_char mcc_mccf;
346 char res3[7];
347 } mcc_t;
348
349 typedef struct comm_proc {
350 uint cp_cpcr;
351 uint cp_rccr;
352 char res1[14];
353 ushort cp_rter;
354 char res2[2];
355 ushort cp_rtmr;
356 ushort cp_rtscr;
357 char res3[2];
358 uint cp_rtsr;
359 char res4[12];
360 } cpm8260_t;
361
362 /* ...and the whole thing wrapped up....
363 */
364 typedef struct immap {
365 /* Some references are into the unique and known dpram spaces,
366 * others are from the generic base.
367 */
368 #define im_dprambase im_dpram1
369 u_char im_dpram1[16*1024];
370 char res1[16*1024];
371 u_char im_dpram2[4*1024];
372 char res2[8*1024];
373 u_char im_dpram3[4*1024];
374 char res3[16*1024];
375
376 sysconf8260_t im_siu_conf; /* SIU Configuration */
377 memctl8260_t im_memctl; /* Memory Controller */
378 sit8260_t im_sit; /* System Integration Timers */
379 intctl8260_t im_intctl; /* Interrupt Controller */
380 car8260_t im_clkrst; /* Clocks and reset */
381 iop8260_t im_ioport; /* IO Port control/status */
382 cpmtimer8260_t im_cpmtimer; /* CPM timers */
383 sdma8260_t im_sdma; /* SDMA control/status */
384
385 fcc_t im_fcc[3]; /* Three FCCs */
386
387 char res4[159];
388
389 /* First set of baud rate generators.
390 */
391 char res4a[496];
392 uint im_brgc5;
393 uint im_brgc6;
394 uint im_brgc7;
395 uint im_brgc8;
396
397 char res5[608];
398
399 i2c8260_t im_i2c; /* I2C control/status */
400 cpm8260_t im_cpm; /* Communication processor */
401
402 /* Second set of baud rate generators.
403 */
404 uint im_brgc1;
405 uint im_brgc2;
406 uint im_brgc3;
407 uint im_brgc4;
408
409 scc_t im_scc[4]; /* Four SCCs */
410 smc_t im_smc[2]; /* Couple of SMCs */
411 spi_t im_spi; /* A SPI */
412 cpmux_t im_cpmux; /* CPM clock route mux */
413 siramctl_t im_siramctl1; /* First SI RAM Control */
414 mcc_t im_mcc1; /* First MCC */
415 siramctl_t im_siramctl2; /* Second SI RAM Control */
416 mcc_t im_mcc2; /* Second MCC */
417
418 char res6[1184];
419
420 ushort im_si1txram[256];
421 char res7[512];
422 ushort im_si1rxram[256];
423 char res8[512];
424 ushort im_si2txram[256];
425 char res9[512];
426 ushort im_si2rxram[256];
427 char res10[512];
428 char res11[4096];
429 } immap_t;
430
431 /* The 8260 relies heavily on the IMMR, so we keep it around as a
432 * kernel global symbol now. Should have done this for the 8xx......
433 */
434 immap_t *immr;
435
436 #endif /* __IMMAP_82XX__ */
437 #endif /* __KERNEL__ */
438
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