1 #ifdef __KERNEL__
2 #ifndef _PPC_IO_H
3 #define _PPC_IO_H
4
5 #include <linux/config.h>
6 #include <asm/page.h>
7 #include <asm/byteorder.h>
8
9 #define SIO_CONFIG_RA 0x398
10 #define SIO_CONFIG_RD 0x399
11
12 #define SLOW_DOWN_IO
13
14 #define PMAC_ISA_MEM_BASE 0
15 #define PMAC_PCI_DRAM_OFFSET 0
16 #define CHRP_ISA_IO_BASE 0xf8000000
17 #define CHRP_ISA_MEM_BASE 0xf7000000
18 #define CHRP_PCI_DRAM_OFFSET 0
19 #define PREP_ISA_IO_BASE 0x80000000
20 #define PREP_ISA_MEM_BASE 0xc0000000
21 #define PREP_PCI_DRAM_OFFSET 0x80000000
22
23 #if defined(CONFIG_4xx)
24 #include <asm/board.h>
25 #elif defined(CONFIG_8xx)
26 #include <asm/mpc8xx.h>
27 #elif defined(CONFIG_8260)
28 #include <asm/mpc8260.h>
29 #else /* 4xx/8xx/8260 */
30 #ifdef CONFIG_APUS
31 #define _IO_BASE 0
32 #define _ISA_MEM_BASE 0
33 #define PCI_DRAM_OFFSET 0
34 #else /* CONFIG_APUS */
35 extern unsigned long isa_io_base;
36 extern unsigned long isa_mem_base;
37 extern unsigned long pci_dram_offset;
38 #define _IO_BASE isa_io_base
39 #define _ISA_MEM_BASE isa_mem_base
40 #define PCI_DRAM_OFFSET pci_dram_offset
41 #endif /* CONFIG_APUS */
42 #endif
43
44 #define readb(addr) in_8((volatile u8 *)(addr))
45 #define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
46 #if defined(CONFIG_APUS)
47 #define readw(addr) (*(volatile u16 *) (addr))
48 #define readl(addr) (*(volatile u32 *) (addr))
49 #define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
50 #define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
51 #else
52 #define readw(addr) in_le16((volatile u16 *)(addr))
53 #define readl(addr) in_le32((volatile u32 *)(addr))
54 #define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
55 #define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
56 #endif
57
58
59 #define __raw_readb(addr) (*(volatile unsigned char *)(addr))
60 #define __raw_readw(addr) (*(volatile unsigned short *)(addr))
61 #define __raw_readl(addr) (*(volatile unsigned int *)(addr))
62 #define __raw_writeb(v, addr) (*(volatile unsigned char *)(addr) = (v))
63 #define __raw_writew(v, addr) (*(volatile unsigned short *)(addr) = (v))
64 #define __raw_writel(v, addr) (*(volatile unsigned int *)(addr) = (v))
65
66 /*
67 * The insw/outsw/insl/outsl macros don't do byte-swapping.
68 * They are only used in practice for transferring buffers which
69 * are arrays of bytes, and byte-swapping is not appropriate in
70 * that case. - paulus
71 */
72 #define insb(port, buf, ns) _insb((u8 *)((port)+_IO_BASE), (buf), (ns))
73 #define outsb(port, buf, ns) _outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
74 #define insw(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
75 #define outsw(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
76 #define insl(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
77 #define outsl(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
78
79 #ifdef CONFIG_ALL_PPC
80 /*
81 * We have to handle possible machine checks here on powermacs
82 * and potentially some CHRPs -- paulus.
83 */
84 #define __do_in_asm(name, op) \
85 extern __inline__ unsigned int name(unsigned int port) \
86 { \
87 unsigned int x; \
88 __asm__ __volatile__( \
89 op " %0,0,%1\n" \
90 "1: sync\n" \
91 "2:\n" \
92 ".section .fixup,\"ax\"\n" \
93 "3: li %0,-1\n" \
94 " b 2b\n" \
95 ".previous\n" \
96 ".section __ex_table,\"a\"\n" \
97 " .align 2\n" \
98 " .long 1b,3b\n" \
99 ".previous" \
100 : "=&r" (x) \
101 : "r" (port + _IO_BASE)); \
102 return x; \
103 }
104
105 #define __do_out_asm(name, op) \
106 extern __inline__ void name(unsigned int val, unsigned int port) \
107 { \
108 __asm__ __volatile__( \
109 op " %0,0,%1\n" \
110 "1: sync\n" \
111 "2:\n" \
112 ".section __ex_table,\"a\"\n" \
113 " .align 2\n" \
114 " .long 1b,2b\n" \
115 ".previous" \
116 : : "r" (val), "r" (port + _IO_BASE)); \
117 }
118
119 __do_in_asm(inb, "lbzx")
120 __do_in_asm(inw, "lhbrx")
121 __do_in_asm(inl, "lwbrx")
122 __do_out_asm(outb, "stbx")
123 __do_out_asm(outw, "sthbrx")
124 __do_out_asm(outl, "stwbrx")
125
126 #elif defined(CONFIG_APUS)
127 #define inb(port) in_8((u8 *)((port)+_IO_BASE))
128 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
129 #define inw(port) in_be16((u16 *)((port)+_IO_BASE))
130 #define outw(val, port) out_be16((u16 *)((port)+_IO_BASE), (val))
131 #define inl(port) in_be32((u32 *)((port)+_IO_BASE))
132 #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val))
133
134 #else /* not APUS or ALL_PPC */
135 #define inb(port) in_8((u8 *)((port)+_IO_BASE))
136 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val))
137 #define inw(port) in_le16((u16 *)((port)+_IO_BASE))
138 #define outw(val, port) out_le16((u16 *)((port)+_IO_BASE), (val))
139 #define inl(port) in_le32((u32 *)((port)+_IO_BASE))
140 #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val))
141 #endif
142
143 #define inb_p(port) inb((port))
144 #define outb_p(val, port) outb((val), (port))
145 #define inw_p(port) inw((port))
146 #define outw_p(val, port) outw((val), (port))
147 #define inl_p(port) inl((port))
148 #define outl_p(val, port) outl((val), (port))
149
150 extern void _insb(volatile u8 *port, void *buf, int ns);
151 extern void _outsb(volatile u8 *port, const void *buf, int ns);
152 extern void _insw(volatile u16 *port, void *buf, int ns);
153 extern void _outsw(volatile u16 *port, const void *buf, int ns);
154 extern void _insl(volatile u32 *port, void *buf, int nl);
155 extern void _outsl(volatile u32 *port, const void *buf, int nl);
156 extern void _insw_ns(volatile u16 *port, void *buf, int ns);
157 extern void _outsw_ns(volatile u16 *port, const void *buf, int ns);
158 extern void _insl_ns(volatile u32 *port, void *buf, int nl);
159 extern void _outsl_ns(volatile u32 *port, const void *buf, int nl);
160
161 /*
162 * The *_ns versions below don't do byte-swapping.
163 * Neither do the standard versions now, these are just here
164 * for older code.
165 */
166 #define insw_ns(port, buf, ns) _insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
167 #define outsw_ns(port, buf, ns) _outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
168 #define insl_ns(port, buf, nl) _insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
169 #define outsl_ns(port, buf, nl) _outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
170
171
172 #define IO_SPACE_LIMIT ~0
173
174 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
175 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
176 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
177
178 #ifdef __KERNEL__
179 /*
180 * Map in an area of physical address space, for accessing
181 * I/O devices etc.
182 */
183 extern void *__ioremap(unsigned long address, unsigned long size,
184 unsigned long flags);
185 extern void *__ioremap_at(unsigned long phys, unsigned long size,
186 unsigned long flags);
187 extern void *ioremap(unsigned long address, unsigned long size);
188 #define ioremap_nocache(addr, size) ioremap((addr), (size))
189 extern void iounmap(void *addr);
190 extern unsigned long iopa(unsigned long addr);
191 #ifdef CONFIG_APUS
192 extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
193 #endif
194
195 /*
196 * The PCI bus is inherently Little-Endian. The PowerPC is being
197 * run Big-Endian. Thus all values which cross the [PCI] barrier
198 * must be endian-adjusted. Also, the local DRAM has a different
199 * address from the PCI point of view, thus buffer addresses also
200 * have to be modified [mapped] appropriately.
201 */
202 extern inline unsigned long virt_to_bus(volatile void * address)
203 {
204 #ifndef CONFIG_APUS
205 if (address == (void *)0)
206 return 0;
207 return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
208 #else
209 return iopa ((unsigned long) address);
210 #endif
211 }
212
213 extern inline void * bus_to_virt(unsigned long address)
214 {
215 #ifndef CONFIG_APUS
216 if (address == 0)
217 return 0;
218 return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
219 #else
220 return (void*) mm_ptov (address);
221 #endif
222 }
223
224 /*
225 * The PCI bus bridge can translate addresses issued by the processor(s)
226 * into a different address on the PCI bus. On 32-bit cpus, we assume
227 * this mapping is 1-1, but on 64-bit systems it often isn't.
228 */
229 #ifndef CONFIG_PPC64BRIDGE
230 #define phys_to_bus(x) (x)
231 #define bus_to_phys(x) (x)
232
233 #else
234 extern unsigned long phys_to_bus(unsigned long pa);
235 extern unsigned long bus_to_phys(unsigned int ba, int busnr);
236 #endif /* CONFIG_PPC64BRIDGE */
237
238 /*
239 * Change virtual addresses to physical addresses and vv, for
240 * addresses in the area where the kernel has the RAM mapped.
241 */
242 extern inline unsigned long virt_to_phys(volatile void * address)
243 {
244 #ifndef CONFIG_APUS
245 return (unsigned long) address - KERNELBASE;
246 #else
247 return iopa ((unsigned long) address);
248 #endif
249 }
250
251 extern inline void * phys_to_virt(unsigned long address)
252 {
253 #ifndef CONFIG_APUS
254 return (void *) (address + KERNELBASE);
255 #else
256 return (void*) mm_ptov (address);
257 #endif
258 }
259
260 #endif /* __KERNEL__ */
261
262 /*
263 * Enforce In-order Execution of I/O:
264 * Acts as a barrier to ensure all previous I/O accesses have
265 * completed before any further ones are issued.
266 */
267 extern inline void eieio(void)
268 {
269 __asm__ __volatile__ ("eieio" : : : "memory");
270 }
271
272 /* Enforce in-order execution of data I/O.
273 * No distinction between read/write on PPC; use eieio for all three.
274 */
275 #define iobarrier_rw() eieio()
276 #define iobarrier_r() eieio()
277 #define iobarrier_w() eieio()
278
279 /*
280 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
281 */
282 extern inline int in_8(volatile unsigned char *addr)
283 {
284 int ret;
285
286 __asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
287 return ret;
288 }
289
290 extern inline void out_8(volatile unsigned char *addr, int val)
291 {
292 __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
293 }
294
295 extern inline int in_le16(volatile unsigned short *addr)
296 {
297 int ret;
298
299 __asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
300 "r" (addr), "m" (*addr));
301 return ret;
302 }
303
304 extern inline int in_be16(volatile unsigned short *addr)
305 {
306 int ret;
307
308 __asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
309 return ret;
310 }
311
312 extern inline void out_le16(volatile unsigned short *addr, int val)
313 {
314 __asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
315 "r" (val), "r" (addr));
316 }
317
318 extern inline void out_be16(volatile unsigned short *addr, int val)
319 {
320 __asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
321 }
322
323 extern inline unsigned in_le32(volatile unsigned *addr)
324 {
325 unsigned ret;
326
327 __asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
328 "r" (addr), "m" (*addr));
329 return ret;
330 }
331
332 extern inline unsigned in_be32(volatile unsigned *addr)
333 {
334 unsigned ret;
335
336 __asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
337 return ret;
338 }
339
340 extern inline void out_le32(volatile unsigned *addr, int val)
341 {
342 __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
343 "r" (val), "r" (addr));
344 }
345
346 extern inline void out_be32(volatile unsigned *addr, int val)
347 {
348 __asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
349 }
350
351 static inline int check_signature(unsigned long io_addr,
352 const unsigned char *signature, int length)
353 {
354 int retval = 0;
355 do {
356 if (readb(io_addr) != *signature)
357 goto out;
358 io_addr++;
359 signature++;
360 length--;
361 } while (length);
362 retval = 1;
363 out:
364 return retval;
365 }
366
367 /* Nothing to do */
368
369 #define dma_cache_inv(_start,_size) do { } while (0)
370 #define dma_cache_wback(_start,_size) do { } while (0)
371 #define dma_cache_wback_inv(_start,_size) do { } while (0)
372
373 #endif
374 #endif /* __KERNEL__ */
375
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