1 #ifdef __KERNEL__
2 #ifndef _ASM_IRQ_H
3 #define _ASM_IRQ_H
4
5 #include <linux/config.h>
6 #include <asm/machdep.h> /* ppc_md */
7
8 extern void disable_irq(unsigned int);
9 extern void disable_irq_nosync(unsigned int);
10 extern void enable_irq(unsigned int);
11
12 #if defined(CONFIG_4xx)
13
14 /*
15 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
16 * 32 possible interrupts, a majority of which are not implemented on
17 * all cores. There are six configurable, external interrupt pins and
18 * there are eight internal interrupts for the on-chip serial port
19 * (SPU), DMA controller, and JTAG controller.
20 *
21 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
22 * possible interrupts as well. There are seven, configurable external
23 * interrupt pins and there are 17 internal interrupts for the on-chip
24 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
25 *
26 */
27
28 #define NR_IRQS 32
29
30 #define AIC_INT0 (0)
31 #define AIC_INT4 (4)
32 #define AIC_INT5 (5)
33 #define AIC_INT6 (6)
34 #define AIC_INT7 (7)
35 #define AIC_INT8 (8)
36 #define AIC_INT9 (9)
37 #define AIC_INT10 (10)
38 #define AIC_INT11 (11)
39 #define AIC_INT27 (27)
40 #define AIC_INT28 (28)
41 #define AIC_INT29 (29)
42 #define AIC_INT30 (30)
43 #define AIC_INT31 (31)
44
45
46 static __inline__ int
47 irq_cannonicalize(int irq)
48 {
49 return (irq);
50 }
51
52 #elif defined(CONFIG_8xx)
53
54 /* The MPC8xx cores have 16 possible interrupts. There are eight
55 * possible level sensitive interrupts assigned and generated internally
56 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
57 * There are eight external interrupts (IRQs) that can be configured
58 * as either level or edge sensitive.
59 *
60 * On some implementations, there is also the possibility of an 8259
61 * through the PCI and PCI-ISA bridges.
62 */
63 #define NR_SIU_INTS 16
64
65 #define NR_IRQS (NR_SIU_INTS + NR_8259_INTS)
66
67 /* These values must be zero-based and map 1:1 with the SIU configuration.
68 * They are used throughout the 8xx I/O subsystem to generate
69 * interrupt masks, flags, and other control patterns. This is why the
70 * current kernel assumption of the 8259 as the base controller is such
71 * a pain in the butt.
72 */
73 #define SIU_IRQ0 (0) /* Highest priority */
74 #define SIU_LEVEL0 (1)
75 #define SIU_IRQ1 (2)
76 #define SIU_LEVEL1 (3)
77 #define SIU_IRQ2 (4)
78 #define SIU_LEVEL2 (5)
79 #define SIU_IRQ3 (6)
80 #define SIU_LEVEL3 (7)
81 #define SIU_IRQ4 (8)
82 #define SIU_LEVEL4 (9)
83 #define SIU_IRQ5 (10)
84 #define SIU_LEVEL5 (11)
85 #define SIU_IRQ6 (12)
86 #define SIU_LEVEL6 (13)
87 #define SIU_IRQ7 (14)
88 #define SIU_LEVEL7 (15)
89
90 /* The internal interrupts we can configure as we see fit.
91 * My personal preference is CPM at level 2, which puts it above the
92 * MBX PCI/ISA/IDE interrupts.
93 */
94 #define PIT_INTERRUPT SIU_LEVEL0
95 #define CPM_INTERRUPT SIU_LEVEL2
96 #define PCMCIA_INTERRUPT SIU_LEVEL6
97 #define DEC_INTERRUPT SIU_LEVEL7
98
99 /* Some internal interrupt registers use an 8-bit mask for the interrupt
100 * level instead of a number.
101 */
102 #define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
103
104 /* Now include the board configuration specific associations.
105 */
106 #include <asm/mpc8xx.h>
107
108 /* always the same on 8xx -- Cort */
109 static __inline__ int irq_cannonicalize(int irq)
110 {
111 return irq;
112 }
113
114 #else /* CONFIG_4xx + CONFIG_8xx */
115
116 #if defined(CONFIG_APUS)
117 /*
118 * This structure is used to chain together the ISRs for a particular
119 * interrupt source (if it supports chaining).
120 */
121 typedef struct irq_node {
122 void (*handler)(int, void *, struct pt_regs *);
123 unsigned long flags;
124 void *dev_id;
125 const char *devname;
126 struct irq_node *next;
127 } irq_node_t;
128
129 /*
130 * This structure has only 4 elements for speed reasons
131 */
132 typedef struct irq_handler {
133 void (*handler)(int, void *, struct pt_regs *);
134 unsigned long flags;
135 void *dev_id;
136 const char *devname;
137 } irq_handler_t;
138
139 /* count of spurious interrupts */
140 extern volatile unsigned int num_spurious;
141
142 extern int sys_request_irq(unsigned int,
143 void (*)(int, void *, struct pt_regs *),
144 unsigned long, const char *, void *);
145 extern void sys_free_irq(unsigned int, void *);
146
147 /*
148 * This function returns a new irq_node_t
149 */
150 extern irq_node_t *new_irq_node(void);
151
152 /* Number of m68k interrupts */
153 #define SYS_IRQS 8
154
155 #endif /* CONFIG_APUS */
156
157 /*
158 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
159 * so it is the max of them all
160 */
161 #define NR_IRQS 256
162
163 #ifndef CONFIG_8260
164
165 #define NUM_8259_INTERRUPTS 16
166 #define IRQ_8259_CASCADE 16
167 #define openpic_to_irq(n) ((n)+NUM_8259_INTERRUPTS)
168 #define irq_to_openpic(n) ((n)-NUM_8259_INTERRUPTS)
169
170 #else /* CONFIG_8260 */
171
172 /* The 8260 has an internal interrupt controller with a maximum of
173 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
174 * Don't be confused by the 8260 documentation where they list an
175 * "interrupt number" and "interrupt vector". We are only interested
176 * in the interrupt vector. There are "reserved" holes where the
177 * vector number increases, but the interrupt number in the table does not.
178 * (Document errata updates have fixed this...make sure you have up to
179 * date processor documentation -- Dan).
180 */
181 #define NR_SIU_INTS 64
182
183 /* There are many more than these, we will add them as we need them.
184 */
185 #define SIU_INT_SMC1 ((uint)0x04)
186 #define SIU_INT_SMC2 ((uint)0x05)
187 #define SIU_INT_FCC1 ((uint)0x20)
188 #define SIU_INT_FCC2 ((uint)0x21)
189 #define SIU_INT_FCC3 ((uint)0x22)
190 #define SIU_INT_SCC1 ((uint)0x28)
191 #define SIU_INT_SCC2 ((uint)0x29)
192 #define SIU_INT_SCC3 ((uint)0x2a)
193 #define SIU_INT_SCC4 ((uint)0x2b)
194
195 #endif /* CONFIG_8260 */
196
197 /*
198 * This gets called from serial.c, which is now used on
199 * powermacs as well as prep/chrp boxes.
200 * Prep and chrp both have cascaded 8259 PICs.
201 */
202 static __inline__ int irq_cannonicalize(int irq)
203 {
204 if (ppc_md.irq_cannonicalize)
205 {
206 return ppc_md.irq_cannonicalize(irq);
207 }
208 else
209 {
210 return irq;
211 }
212 }
213
214 #endif
215
216 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
217 extern unsigned int ppc_lost_interrupts[NR_MASK_WORDS];
218
219 #endif /* _ASM_IRQ_H */
220 #endif /* __KERNEL__ */
221
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