1 /*
2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
3 *
4 */
5
6 /* offset from base for feature control registers */
7 #define KEYLARGO_MBCR 0x34 /* Media bay control/status */
8 #define KEYLARGO_FCR0 0x38
9 #define KEYLARGO_FCR1 0x3c
10 #define KEYLARGO_FCR2 0x40
11 #define KEYLARGO_FCR3 0x44
12 #define KEYLARGO_FCR4 0x48
13
14 /* GPIO registers */
15 #define KEYLARGO_GPIO_LEVELS0 0x50
16 #define KEYLARGO_GPIO_LEVELS1 0x54
17 #define KEYLARGO_GPIO_EXTINT_0 0x58
18 #define KEYLARGO_GPIO_EXTINT_CNT 18
19 #define KEYLARGO_GPIO_0 0x6A
20 #define KEYLARGO_GPIO_CNT 17
21
22 /* Specific GPIO regs */
23 #define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
24 #define KL_GPIO_ETH_PHY_RESET_ASSERT 0x04
25 #define KL_GPIO_ETH_PHY_RESET_RELEASE 0x05
26 #define KL_GPIO_ETH_PHY_RESET_TRISTATE 0x00
27 /*
28 * Bits in feature control register
29 */
30 #define KL_MBCR_MBDEV_ENABLE 0x00001000
31
32 #define KL0_SCC_B_INTF_ENABLE 0x00000001 /* ??? */
33 #define KL0_SCC_A_INTF_ENABLE 0x00000002 /* ??? */
34 #define KL0_SCC_SLOWPCLK 0x00000004
35 #define KL0_SCC_RESET 0x00000008
36 #define KL0_SCCA_ENABLE 0x00000010
37 #define KL0_SCCB_ENABLE 0x00000020
38 #define KL0_SCC_CELL_ENABLE 0x00000040
39 #define KL0_IRDA_ENABLE 0x00008000
40 #define KL0_IRDA_CLK32_ENABLE 0x00010000
41 #define KL0_IRDA_CLK19_ENABLE 0x00020000
42 #define KL0_USB0_PAD_SUSPEND0 0x00040000
43 #define KL0_USB0_PAD_SUSPEND1 0x00080000
44 #define KL0_USB0_CELL_ENABLE 0x00100000
45 #define KL0_USB1_PAD_SUSPEND0 0x00400000
46 #define KL0_USB1_PAD_SUSPEND1 0x00800000
47 #define KL0_USB1_CELL_ENABLE 0x01000000
48 #define KL0_USB_REF_SUSPEND 0x10000000
49
50 #define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
51 KL0_SCC_SLOWPCLK | \
52 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
53
54 #define KL1_AUDIO_SEL_22MCLK 0x00000002
55 #define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008
56 #define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* Burgundy only ? */
57 #define KL1_AUDIO_CELL_ENABLE 0x00000040
58 #define KL1_AUDIO_CHOOSE 0x00000080 /* Burgundy only ? */
59 #define KL1_I2S0_CELL_ENABLE 0x00000400
60 #define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
61 #define KL1_I2S0_ENABLE 0x00002000
62 #define KL1_I2S1_CELL_ENABLE 0x00020000
63 #define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
64 #define KL1_I2S1_ENABLE 0x00100000
65 #define KL1_EIDE0_ENABLE 0x00800000
66 #define KL1_EIDE0_RESET_N 0x01000000
67 #define KL1_EIDE1_ENABLE 0x04000000
68 #define KL1_EIDE1_RESET_N 0x08000000
69 #define KL1_UIDE_ENABLE 0x20000000
70 #define KL1_UIDE_RESET_N 0x40000000
71
72 #define KL2_IOBUS_ENABLE 0x00000002
73 #define KL2_SLEEP_STATE_BIT 0x00000100
74 #define KL2_MPIC_ENABLE 0x00020000
75 #define KL2_MODEM_POWER_N 0x02000000
76 #define KL2_AIRPORT_RESET_N 0x08000000 /* Or power ? */
77
78 #define KL3_SHUTDOWN_PLL_TOTAL 0x00000001
79 #define KL3_SHUTDOWN_PLLKW6 0x00000002
80 #define KL3_SHUTDOWN_PLLKW4 0x00000004
81 #define KL3_SHUTDOWN_PLLKW35 0x00000008
82 #define KL3_SHUTDOWN_PLLKW12 0x00000010
83 #define KL3_PLL_RESET 0x00000020
84 #define KL3_SHUTDOWN_PLL2X 0x00000080
85 #define KL3_CLK66_ENABLE 0x00000100
86 #define KL3_CLK49_ENABLE 0x00000200
87 #define KL3_CLK45_ENABLE 0x00000400
88 #define KL3_CLK31_ENABLE 0x00000800
89 #define KL3_TIMER_CLK18_ENABLE 0x00001000
90 #define KL3_I2S1_CLK18_ENABLE 0x00002000
91 #define KL3_I2S0_CLK18_ENABLE 0x00004000
92 #define KL3_VIA_CLK16_ENABLE 0x00008000
93 #define KL3_STOPPING33_ENABLED 0x00080000
94
95 /* Port 0,1 : bus 0, port 2,3 : bus 1 */
96 #define KL4_SET_PORT_ENABLE(p) (0x00000008 << (p<<3))
97 #define KL4_SET_PORT_RESUME(p) (0x00000004 << (p<<3))
98 #define KL4_SET_PORT_CONNECT(p) (0x00000002 << (p<<3))
99 #define KL4_SET_PORT_DISCONNECT(p) (0x00000001 << (p<<3))
100 #define KL4_GET_PORT_RESUME(p) (0x00000040 << (p<<3))
101 #define KL4_GET_PORT_CONNECT(p) (0x00000020 << (p<<3))
102 #define KL4_GET_PORT_DISCONNECT(p) (0x00000010 << (p<<3))
103
104
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