1 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola MBX boards. This was originally created for the
4 * MBX860, and probably needs revisions for other boards (like the 821).
5 * When this file gets out of control, we can split it up into more
6 * meaningful pieces.
7 *
8 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
9 */
10 #ifdef __KERNEL__
11 #ifndef __MACH_MBX_DEFS
12 #define __MACH_MBX_DEFS
13
14 /* A Board Information structure that is given to a program when
15 * EPPC-Bug starts it up.
16 */
17 typedef struct bd_info {
18 unsigned int bi_tag; /* Should be 0x42444944 "BDID" */
19 unsigned int bi_size; /* Size of this structure */
20 unsigned int bi_revision; /* revision of this structure */
21 unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */
22 unsigned int bi_memstart; /* Memory start address */
23 unsigned int bi_memsize; /* Memory (end) size in bytes */
24 unsigned int bi_intfreq; /* Internal Freq, in Hz */
25 unsigned int bi_busfreq; /* Bus Freq, in Hz */
26 unsigned int bi_clun; /* Boot device controller */
27 unsigned int bi_dlun; /* Boot device logical dev */
28 unsigned int bi_baudrate; /* ...to be like everyone else */
29 } bd_t;
30
31 /* Memory map for the MBX as configured by EPPC-Bug. We could reprogram
32 * The SIU and PCI bridge, and try to use larger MMU pages, but the
33 * performance gain is not measureable and it certainly complicates the
34 * generic MMU model.
35 *
36 * In a effort to minimize memory usage for embedded applications, any
37 * PCI driver or ISA driver must request or map the region required by
38 * the device. For convenience (and since we can map up to 4 Mbytes with
39 * a single page table page), the MMU initialization will map the
40 * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
41 * Bridge CSRs 1:1 into the kernel address space.
42 */
43 #define PCI_ISA_IO_ADDR ((unsigned)0x80000000)
44 #define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024))
45 #define PCI_IDE_ADDR ((unsigned)0x81000000)
46 #define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000)
47 #define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024))
48 #define PCMCIA_MEM_ADDR ((uint)0xe0000000)
49 #define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024))
50 #define PCMCIA_DMA_ADDR ((uint)0xe4000000)
51 #define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024))
52 #define PCMCIA_ATTRB_ADDR ((uint)0xe8000000)
53 #define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024))
54 #define PCMCIA_IO_ADDR ((uint)0xec000000)
55 #define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024))
56 #define NVRAM_ADDR ((uint)0xfa000000)
57 #define NVRAM_SIZE ((uint)(1 * 1024 * 1024))
58 #define MBX_CSR_ADDR ((uint)0xfa100000)
59 #define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024))
60 #define IMAP_ADDR ((uint)0xfa200000)
61 #define IMAP_SIZE ((uint)(64 * 1024))
62 #define PCI_CSR_ADDR ((uint)0xfa210000)
63 #define PCI_CSR_SIZE ((uint)(64 * 1024))
64
65 /* Map additional physical space into well known virtual addresses. Due
66 * to virtual address mapping, these physical addresses are not accessible
67 * in a 1:1 virtual to physical mapping.
68 */
69 #define ISA_IO_VIRT_ADDR ((uint)0xfa220000)
70 #define ISA_IO_VIRT_SIZE ((uint)64 * 1024)
71
72 /* Interrupt assignments.
73 * These are defined (and fixed) by the MBX hardware implementation.
74 */
75 #define POWER_FAIL_INT SIU_IRQ0 /* Power fail */
76 #define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */
77 #define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */
78 #define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */
79 #define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */
80 #define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */
81
82 /* The MBX uses the 8259.
83 */
84 #define NR_8259_INTS 16
85
86 /* Generic 8xx type
87 */
88 #define _MACH_8xx (_MACH_mbx)
89 #endif
90 #endif /* __KERNEL__ */
91
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