1 /*
2 * PowerPC memory management structures
3 */
4
5 #ifdef __KERNEL__
6 #ifndef _PPC_MMU_H_
7 #define _PPC_MMU_H_
8
9 /* Default "unsigned long" context */
10 typedef unsigned long mm_context_t;
11
12 #include <linux/config.h>
13
14 #ifndef __ASSEMBLY__
15 /* Hardware Page Table Entry */
16 typedef struct _PTE {
17 #ifdef CONFIG_PPC64BRIDGE
18 unsigned long long vsid:52;
19 unsigned long api:5;
20 unsigned long :5;
21 unsigned long h:1;
22 unsigned long v:1;
23 unsigned long long rpn:52;
24 #else /* CONFIG_PPC64BRIDGE */
25 unsigned long v:1; /* Entry is valid */
26 unsigned long vsid:24; /* Virtual segment identifier */
27 unsigned long h:1; /* Hash algorithm indicator */
28 unsigned long api:6; /* Abbreviated page index */
29 unsigned long rpn:20; /* Real (physical) page number */
30 #endif /* CONFIG_PPC64BRIDGE */
31 unsigned long :3; /* Unused */
32 unsigned long r:1; /* Referenced */
33 unsigned long c:1; /* Changed */
34 unsigned long w:1; /* Write-thru cache mode */
35 unsigned long i:1; /* Cache inhibited */
36 unsigned long m:1; /* Memory coherence */
37 unsigned long g:1; /* Guarded */
38 unsigned long :1; /* Unused */
39 unsigned long pp:2; /* Page protection */
40 } PTE;
41
42 /* Values for PP (assumes Ks=0, Kp=1) */
43 #define PP_RWXX 0 /* Supervisor read/write, User none */
44 #define PP_RWRX 1 /* Supervisor read/write, User read */
45 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
46 #define PP_RXRX 3 /* Supervisor read, User read */
47
48 /* Segment Register */
49 typedef struct _SEGREG {
50 unsigned long t:1; /* Normal or I/O type */
51 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
52 unsigned long kp:1; /* User 'key' (normally 1) */
53 unsigned long n:1; /* No-execute */
54 unsigned long :4; /* Unused */
55 unsigned long vsid:24; /* Virtual Segment Identifier */
56 } SEGREG;
57
58 /* Block Address Translation (BAT) Registers */
59 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
60 unsigned long bepi:15; /* Effective page index (virtual address) */
61 unsigned long :8; /* unused */
62 unsigned long w:1;
63 unsigned long i:1; /* Cache inhibit */
64 unsigned long m:1; /* Memory coherence */
65 unsigned long ks:1; /* Supervisor key (normally 0) */
66 unsigned long kp:1; /* User key (normally 1) */
67 unsigned long pp:2; /* Page access protections */
68 } P601_BATU;
69
70 typedef struct _BATU { /* Upper part of BAT (all except 601) */
71 #ifdef CONFIG_PPC64BRIDGE
72 unsigned long long bepi:47;
73 #else /* CONFIG_PPC64BRIDGE */
74 unsigned long bepi:15; /* Effective page index (virtual address) */
75 #endif /* CONFIG_PPC64BRIDGE */
76 unsigned long :4; /* Unused */
77 unsigned long bl:11; /* Block size mask */
78 unsigned long vs:1; /* Supervisor valid */
79 unsigned long vp:1; /* User valid */
80 } BATU;
81
82 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
83 unsigned long brpn:15; /* Real page index (physical address) */
84 unsigned long :10; /* Unused */
85 unsigned long v:1; /* Valid bit */
86 unsigned long bl:6; /* Block size mask */
87 } P601_BATL;
88
89 typedef struct _BATL { /* Lower part of BAT (all except 601) */
90 #ifdef CONFIG_PPC64BRIDGE
91 unsigned long long brpn:47;
92 #else /* CONFIG_PPC64BRIDGE */
93 unsigned long brpn:15; /* Real page index (physical address) */
94 #endif /* CONFIG_PPC64BRIDGE */
95 unsigned long :10; /* Unused */
96 unsigned long w:1; /* Write-thru cache */
97 unsigned long i:1; /* Cache inhibit */
98 unsigned long m:1; /* Memory coherence */
99 unsigned long g:1; /* Guarded (MBZ in IBAT) */
100 unsigned long :1; /* Unused */
101 unsigned long pp:2; /* Page access protections */
102 } BATL;
103
104 typedef struct _BAT {
105 BATU batu; /* Upper register */
106 BATL batl; /* Lower register */
107 } BAT;
108
109 typedef struct _P601_BAT {
110 P601_BATU batu; /* Upper register */
111 P601_BATL batl; /* Lower register */
112 } P601_BAT;
113
114 /*
115 * Simulated two-level MMU. This structure is used by the kernel
116 * to keep track of MMU mappings and is used to update/maintain
117 * the hardware HASH table which is really a cache of mappings.
118 *
119 * The simulated structures mimic the hardware available on other
120 * platforms, notably the 80x86 and 680x0.
121 */
122
123 typedef struct _pte {
124 unsigned long page_num:20;
125 unsigned long flags:12; /* Page flags (some unused bits) */
126 } pte;
127
128 #define PD_SHIFT (10+12) /* Page directory */
129 #define PD_MASK 0x02FF
130 #define PT_SHIFT (12) /* Page Table */
131 #define PT_MASK 0x02FF
132 #define PG_SHIFT (12) /* Page Entry */
133
134
135 /* MMU context */
136
137 typedef struct _MMU_context {
138 SEGREG segs[16]; /* Segment registers */
139 pte **pmap; /* Two-level page-map structure */
140 } MMU_context;
141
142 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
143 extern void _tlbia(void); /* invalidate all TLB entries */
144
145 #endif /* __ASSEMBLY__ */
146
147 /* Block size masks */
148 #define BL_128K 0x000
149 #define BL_256K 0x001
150 #define BL_512K 0x003
151 #define BL_1M 0x007
152 #define BL_2M 0x00F
153 #define BL_4M 0x01F
154 #define BL_8M 0x03F
155 #define BL_16M 0x07F
156 #define BL_32M 0x0FF
157 #define BL_64M 0x1FF
158 #define BL_128M 0x3FF
159 #define BL_256M 0x7FF
160
161 /* BAT Access Protection */
162 #define BPP_XX 0x00 /* No access */
163 #define BPP_RX 0x01 /* Read only */
164 #define BPP_RW 0x02 /* Read/write */
165
166 /* Used to set up SDR1 register */
167 #define HASH_TABLE_SIZE_64K 0x00010000
168 #define HASH_TABLE_SIZE_128K 0x00020000
169 #define HASH_TABLE_SIZE_256K 0x00040000
170 #define HASH_TABLE_SIZE_512K 0x00080000
171 #define HASH_TABLE_SIZE_1M 0x00100000
172 #define HASH_TABLE_SIZE_2M 0x00200000
173 #define HASH_TABLE_SIZE_4M 0x00400000
174 #define HASH_TABLE_MASK_64K 0x000
175 #define HASH_TABLE_MASK_128K 0x001
176 #define HASH_TABLE_MASK_256K 0x003
177 #define HASH_TABLE_MASK_512K 0x007
178 #define HASH_TABLE_MASK_1M 0x00F
179 #define HASH_TABLE_MASK_2M 0x01F
180 #define HASH_TABLE_MASK_4M 0x03F
181
182 /* Control/status registers for the MPC8xx.
183 * A write operation to these registers causes serialized access.
184 * During software tablewalk, the registers used perform mask/shift-add
185 * operations when written/read. A TLB entry is created when the Mx_RPN
186 * is written, and the contents of several registers are used to
187 * create the entry.
188 */
189 #define MI_CTR 784 /* Instruction TLB control register */
190 #define MI_GPM 0x80000000 /* Set domain manager mode */
191 #define MI_PPM 0x40000000 /* Set subpage protection */
192 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
193 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
194 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
195 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
196 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
197
198 /* These are the Ks and Kp from the PowerPC books. For proper operation,
199 * Ks = 0, Kp = 1.
200 */
201 #define MI_AP 786
202 #define MI_Ks 0x80000000 /* Should not be set */
203 #define MI_Kp 0x40000000 /* Should always be set */
204
205 /* The effective page number register. When read, contains the information
206 * about the last instruction TLB miss. When MI_RPN is written, bits in
207 * this register are used to create the TLB entry.
208 */
209 #define MI_EPN 787
210 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
211 #define MI_EVALID 0x00000200 /* Entry is valid */
212 #define MI_ASIDMASK 0x0000000f /* ASID match value */
213 /* Reset value is undefined */
214
215 /* A "level 1" or "segment" or whatever you want to call it register.
216 * For the instruction TLB, it contains bits that get loaded into the
217 * TLB entry when the MI_RPN is written.
218 */
219 #define MI_TWC 789
220 #define MI_APG 0x000001e0 /* Access protection group (0) */
221 #define MI_GUARDED 0x00000010 /* Guarded storage */
222 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
223 #define MI_PS8MEG 0x0000000c /* 8M page size */
224 #define MI_PS512K 0x00000004 /* 512K page size */
225 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
226 #define MI_SVALID 0x00000001 /* Segment entry is valid */
227 /* Reset value is undefined */
228
229 /* Real page number. Defined by the pte. Writing this register
230 * causes a TLB entry to be created for the instruction TLB, using
231 * additional information from the MI_EPN, and MI_TWC registers.
232 */
233 #define MI_RPN 790
234
235 /* Define an RPN value for mapping kernel memory to large virtual
236 * pages for boot initialization. This has real page number of 0,
237 * large page size, shared page, cache enabled, and valid.
238 * Also mark all subpages valid and write access.
239 */
240 #define MI_BOOTINIT 0x000001fd
241
242 #define MD_CTR 792 /* Data TLB control register */
243 #define MD_GPM 0x80000000 /* Set domain manager mode */
244 #define MD_PPM 0x40000000 /* Set subpage protection */
245 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
246 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
247 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
248 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
249 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
250 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
251 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
252
253 #define M_CASID 793 /* Address space ID (context) to match */
254 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
255
256
257 /* These are the Ks and Kp from the PowerPC books. For proper operation,
258 * Ks = 0, Kp = 1.
259 */
260 #define MD_AP 794
261 #define MD_Ks 0x80000000 /* Should not be set */
262 #define MD_Kp 0x40000000 /* Should always be set */
263
264 /* The effective page number register. When read, contains the information
265 * about the last instruction TLB miss. When MD_RPN is written, bits in
266 * this register are used to create the TLB entry.
267 */
268 #define MD_EPN 795
269 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
270 #define MD_EVALID 0x00000200 /* Entry is valid */
271 #define MD_ASIDMASK 0x0000000f /* ASID match value */
272 /* Reset value is undefined */
273
274 /* The pointer to the base address of the first level page table.
275 * During a software tablewalk, reading this register provides the address
276 * of the entry associated with MD_EPN.
277 */
278 #define M_TWB 796
279 #define M_L1TB 0xfffff000 /* Level 1 table base address */
280 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
281 /* Reset value is undefined */
282
283 /* A "level 1" or "segment" or whatever you want to call it register.
284 * For the data TLB, it contains bits that get loaded into the TLB entry
285 * when the MD_RPN is written. It is also provides the hardware assist
286 * for finding the PTE address during software tablewalk.
287 */
288 #define MD_TWC 797
289 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
290 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
291 #define MD_APG 0x000001e0 /* Access protection group (0) */
292 #define MD_GUARDED 0x00000010 /* Guarded storage */
293 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
294 #define MD_PS8MEG 0x0000000c /* 8M page size */
295 #define MD_PS512K 0x00000004 /* 512K page size */
296 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
297 #define MD_WT 0x00000002 /* Use writethrough page attribute */
298 #define MD_SVALID 0x00000001 /* Segment entry is valid */
299 /* Reset value is undefined */
300
301
302 /* Real page number. Defined by the pte. Writing this register
303 * causes a TLB entry to be created for the data TLB, using
304 * additional information from the MD_EPN, and MD_TWC registers.
305 */
306 #define MD_RPN 798
307
308 /* This is a temporary storage register that could be used to save
309 * a processor working register during a tablewalk.
310 */
311 #define M_TW 799
312
313 /*
314 * At present, all PowerPC 400-class processors share a similar TLB
315 * architecture. The instruction and data sides share a unified,
316 * 64-entry, fully-associative TLB which is maintained totally under
317 * software control. In addition, the instruction side has a
318 * hardware-managed, 4-entry, fully- associative TLB which serves as a
319 * first level to the shared TLB. These two TLBs are known as the UTLB
320 * and ITLB, respectively.
321 */
322
323 #define PPC4XX_TLB_SIZE 64
324
325 /*
326 * TLB entries are defined by a "high" tag portion and a "low" data
327 * portion. On all architectures, the data portion is 32-bits.
328 *
329 * TLB entries are managed entirely under software control by reading,
330 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
331 * instructions.
332 */
333
334 #define TLB_LO 1
335 #define TLB_HI 0
336
337 #define TLB_DATA TLB_LO
338 #define TLB_TAG TLB_HI
339
340 /* Tag portion */
341
342 #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
343 #define TLB_PAGESZ_MASK 0x00000380
344 #define TLB_PAGESZ(x) (((x) & 0x7) << 7)
345 #define PAGESZ_1K 0
346 #define PAGESZ_4K 1
347 #define PAGESZ_16K 2
348 #define PAGESZ_64K 3
349 #define PAGESZ_256K 4
350 #define PAGESZ_1M 5
351 #define PAGESZ_4M 6
352 #define PAGESZ_16M 7
353 #define TLB_VALID 0x00000040 /* Entry is valid */
354
355 /* Data portion */
356
357 #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
358 #define TLB_PERM_MASK 0x00000300
359 #define TLB_EX 0x00000200 /* Instruction execution allowed */
360 #define TLB_WR 0x00000100 /* Writes permitted */
361 #define TLB_ZSEL_MASK 0x000000F0
362 #define TLB_ZSEL(x) (((x) & 0xF) << 4)
363 #define TLB_ATTR_MASK 0x0000000F
364 #define TLB_W 0x00000008 /* Caching is write-through */
365 #define TLB_I 0x00000004 /* Caching is inhibited */
366 #define TLB_M 0x00000002 /* Memory is coherent */
367 #define TLB_G 0x00000001 /* Memory is guarded from prefetch */
368
369 #endif /* _PPC_MMU_H_ */
370 #endif /* __KERNEL__ */
371
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