1 #ifdef __KERNEL__
2 #ifndef _PPC_PGTABLE_H
3 #define _PPC_PGTABLE_H
4
5 #include <linux/config.h>
6
7 #ifndef __ASSEMBLY__
8 #include <linux/sched.h>
9 #include <linux/threads.h>
10 #include <asm/processor.h> /* For TASK_SIZE */
11 #include <asm/mmu.h>
12 #include <asm/page.h>
13
14 #if defined(CONFIG_4xx)
15 extern void local_flush_tlb_all(void);
16 extern void local_flush_tlb_mm(struct mm_struct *mm);
17 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
18 extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
19 unsigned long end);
20 extern inline void flush_hash_page(unsigned context, unsigned long va)
21 { }
22 #elif defined(CONFIG_8xx)
23 #define __tlbia() asm volatile ("tlbia" : : )
24
25 extern inline void local_flush_tlb_all(void)
26 { __tlbia(); }
27 extern inline void local_flush_tlb_mm(struct mm_struct *mm)
28 { __tlbia(); }
29 extern inline void local_flush_tlb_page(struct vm_area_struct *vma,
30 unsigned long vmaddr)
31 { __tlbia(); }
32 extern inline void local_flush_tlb_range(struct mm_struct *mm,
33 unsigned long start, unsigned long end)
34 { __tlbia(); }
35 extern inline void flush_hash_page(unsigned context, unsigned long va)
36 { }
37 #else
38 struct mm_struct;
39 struct vm_area_struct;
40 extern void local_flush_tlb_all(void);
41 extern void local_flush_tlb_mm(struct mm_struct *mm);
42 extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
43 extern void local_flush_tlb_range(struct mm_struct *mm, unsigned long start,
44 unsigned long end);
45 #endif
46
47 #define flush_tlb_all local_flush_tlb_all
48 #define flush_tlb_mm local_flush_tlb_mm
49 #define flush_tlb_page local_flush_tlb_page
50 #define flush_tlb_range local_flush_tlb_range
51
52 extern inline void flush_tlb_pgtables(struct mm_struct *mm,
53 unsigned long start, unsigned long end)
54 {
55 /* PPC has hw page tables. */
56 }
57
58 /*
59 * No cache flushing is required when address mappings are
60 * changed, because the caches on PowerPCs are physically
61 * addressed.
62 * Also, when SMP we use the coherency (M) bit of the
63 * BATs and PTEs. -- Cort
64 */
65 #define flush_cache_all() do { } while (0)
66 #define flush_cache_mm(mm) do { } while (0)
67 #define flush_cache_range(mm, a, b) do { } while (0)
68 #define flush_cache_page(vma, p) do { } while (0)
69 #define flush_icache_page(vma, page) do { } while (0)
70
71 extern void flush_icache_range(unsigned long, unsigned long);
72 extern void __flush_page_to_ram(unsigned long page_va);
73 extern void flush_page_to_ram(struct page *page);
74
75 #define flush_dcache_page(page) do { } while (0)
76
77 extern unsigned long va_to_phys(unsigned long address);
78 extern pte_t *va_to_pte(unsigned long address);
79 extern unsigned long ioremap_bot, ioremap_base;
80 #endif /* __ASSEMBLY__ */
81
82 /*
83 * The PowerPC MMU uses a hash table containing PTEs, together with
84 * a set of 16 segment registers (on 32-bit implementations), to define
85 * the virtual to physical address mapping.
86 *
87 * We use the hash table as an extended TLB, i.e. a cache of currently
88 * active mappings. We maintain a two-level page table tree, much like
89 * that used by the i386, for the sake of the Linux memory management code.
90 * Low-level assembler code in head.S (procedure hash_page) is responsible
91 * for extracting ptes from the tree and putting them into the hash table
92 * when necessary, and updating the accessed and modified bits in the
93 * page table tree.
94 */
95
96 /*
97 * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
98 * We also use the two level tables, but we can put the real bits in them
99 * needed for the TLB and tablewalk. These definitions require Mx_CTR.PPM = 0,
100 * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1. The level 2 descriptor has
101 * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
102 * based upon user/super access. The TLB does not have accessed nor write
103 * protect. We assume that if the TLB get loaded with an entry it is
104 * accessed, and overload the changed bit for write protect. We use
105 * two bits in the software pte that are supposed to be set to zero in
106 * the TLB entry (24 and 25) for these indicators. Although the level 1
107 * descriptor contains the guarded and writethrough/copyback bits, we can
108 * set these at the page level since they get copied from the Mx_TWC
109 * register when the TLB entry is loaded. We will use bit 27 for guard, since
110 * that is where it exists in the MD_TWC, and bit 26 for writethrough.
111 * These will get masked from the level 2 descriptor at TLB load time, and
112 * copied to the MD_TWC before it gets loaded.
113 */
114
115 /*
116 * At present, all PowerPC 400-class processors share a similar TLB
117 * architecture. The instruction and data sides share a unified,
118 * 64-entry, fully-associative TLB which is maintained totally under
119 * software control. In addition, the instruction side has a
120 * hardware-managed, 4-entry, fully-associative TLB which serves as a
121 * first level to the shared TLB. These two TLBs are known as the UTLB
122 * and ITLB, respectively (see "mmu.h" for definitions).
123 */
124
125 /* PMD_SHIFT determines the size of the area mapped by the second-level page tables */
126 #define PMD_SHIFT 22
127 #define PMD_SIZE (1UL << PMD_SHIFT)
128 #define PMD_MASK (~(PMD_SIZE-1))
129
130 /* PGDIR_SHIFT determines what a third-level page table entry can map */
131 #define PGDIR_SHIFT 22
132 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
133 #define PGDIR_MASK (~(PGDIR_SIZE-1))
134
135 /*
136 * entries per page directory level: our page-table tree is two-level, so
137 * we don't really have any PMD directory.
138 */
139 #define PTRS_PER_PTE 1024
140 #define PTRS_PER_PMD 1
141 #define PTRS_PER_PGD 1024
142 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
143 #define FIRST_USER_PGD_NR 0
144
145 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
146 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
147
148 #define pte_ERROR(e) \
149 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
150 #define pmd_ERROR(e) \
151 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
152 #define pgd_ERROR(e) \
153 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
154
155 /*
156 * Just any arbitrary offset to the start of the vmalloc VM area: the
157 * current 64MB value just means that there will be a 64MB "hole" after the
158 * physical memory until the kernel virtual memory starts. That means that
159 * any out-of-bounds memory accesses will hopefully be caught.
160 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
161 * area for the same reason. ;)
162 *
163 * We no longer map larger than phys RAM with the BATs so we don't have
164 * to worry about the VMALLOC_OFFSET causing problems. We do have to worry
165 * about clashes between our early calls to ioremap() that start growing down
166 * from ioremap_base being run into the VM area allocations (growing upwards
167 * from VMALLOC_START). For this reason we have ioremap_bot to check when
168 * we actually run into our mappings setup in the early boot with the VM
169 * system. This really does become a problem for machines with good amounts
170 * of RAM. -- Cort
171 */
172 #define VMALLOC_OFFSET (0x1000000) /* 16M */
173 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
174 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
175 #define VMALLOC_END ioremap_bot
176
177 /*
178 * Bits in a linux-style PTE. These match the bits in the
179 * (hardware-defined) PowerPC PTE as closely as possible.
180 */
181
182 #if defined(CONFIG_4xx)
183 /* Definitions for 4xx embedded chips. */
184 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
185 #define _PAGE_COHERENT 0x002 /* M: enforece memory coherence */
186 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
187 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
188 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
189 #define _PAGE_PRESENT 0x040 /* software: PTE contains a translation */
190 #define _PAGE_DIRTY 0x100 /* C: page changed */
191 #define _PAGE_RW 0x200 /* Writes permitted */
192 #define _PAGE_ACCESSED 0x400 /* R: page referenced */
193 #define _PAGE_HWWRITE 0x800 /* software: _PAGE_RW & _PAGE_DIRTY */
194 #define _PAGE_SHARED 0
195
196 #elif defined(CONFIG_8xx)
197 /* Definitions for 8xx embedded chips. */
198 #define _PAGE_PRESENT 0x0001 /* Page is valid */
199 #define _PAGE_NO_CACHE 0x0002 /* I: cache inhibit */
200 #define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
201
202 /* These five software bits must be masked out when the entry is loaded
203 * into the TLB.
204 */
205 #define _PAGE_DIRTY 0x0008 /* software: page changed */
206 #define _PAGE_GUARDED 0x0010 /* software: guarded access */
207 #define _PAGE_WRITETHRU 0x0020 /* software: use writethrough cache */
208 #define _PAGE_RW 0x0040 /* software: user write access allowed */
209 #define _PAGE_ACCESSED 0x0080 /* software: page referenced */
210
211 #define _PAGE_HWWRITE 0x0100 /* C: page changed (write protect) */
212 #define _PAGE_USER 0x0800 /* One of the PP bits, the other must be 0 */
213
214 #else /* CONFIG_6xx */
215 /* Definitions for 60x, 740/750, etc. */
216 #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
217 #define _PAGE_USER 0x002 /* matches one of the PP bits */
218 #define _PAGE_RW 0x004 /* software: user write access allowed */
219 #define _PAGE_GUARDED 0x008
220 #define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
221 #define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
222 #define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
223 #define _PAGE_DIRTY 0x080 /* C: page changed */
224 #define _PAGE_ACCESSED 0x100 /* R: page referenced */
225 #define _PAGE_HWWRITE 0x200 /* software: _PAGE_RW & _PAGE_DIRTY */
226 #define _PAGE_SHARED 0
227 #endif
228
229 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
230
231 #ifdef CONFIG_SMP
232 #define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT
233 #else
234 #define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED
235 #endif
236 #define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE
237
238 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
239
240 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | \
241 _PAGE_SHARED)
242 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
243 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
244 #define PAGE_KERNEL __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED)
245 #define PAGE_KERNEL_CI __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | \
246 _PAGE_NO_CACHE )
247
248 /*
249 * The PowerPC can only do execute protection on a segment (256MB) basis,
250 * not on a page basis. So we consider execute permission the same as read.
251 * Also, write permissions imply read permissions.
252 * This is the closest we can get..
253 */
254 #define __P000 PAGE_NONE
255 #define __P001 PAGE_READONLY
256 #define __P010 PAGE_COPY
257 #define __P011 PAGE_COPY
258 #define __P100 PAGE_READONLY
259 #define __P101 PAGE_READONLY
260 #define __P110 PAGE_COPY
261 #define __P111 PAGE_COPY
262
263 #define __S000 PAGE_NONE
264 #define __S001 PAGE_READONLY
265 #define __S010 PAGE_SHARED
266 #define __S011 PAGE_SHARED
267 #define __S100 PAGE_READONLY
268 #define __S101 PAGE_READONLY
269 #define __S110 PAGE_SHARED
270 #define __S111 PAGE_SHARED
271
272 #ifndef __ASSEMBLY__
273 /*
274 * ZERO_PAGE is a global shared page that is always zero: used
275 * for zero-mapped memory areas etc..
276 */
277 extern unsigned long empty_zero_page[1024];
278 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
279
280 /*
281 * BAD_PAGETABLE is used when we need a bogus page-table, while
282 * BAD_PAGE is used for a bogus page.
283 *
284 * ZERO_PAGE is a global shared page that is always zero: used
285 * for zero-mapped memory areas etc..
286 */
287 extern pte_t __bad_page(void);
288 extern pte_t * __bad_pagetable(void);
289
290 #define BAD_PAGETABLE __bad_pagetable()
291 #define BAD_PAGE __bad_page()
292 #endif /* __ASSEMBLY__ */
293
294 /* number of bits that fit into a memory pointer */
295 #define BITS_PER_PTR (8*sizeof(unsigned long))
296
297 /* to align the pointer to a pointer address */
298 #define PTR_MASK (~(sizeof(void*)-1))
299
300 /* sizeof(void*) == 1<<SIZEOF_PTR_LOG2 */
301 /* 64-bit machines, beware! SRB. */
302 #define SIZEOF_PTR_LOG2 2
303
304 #define pte_none(pte) (!pte_val(pte))
305 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
306 #define pte_clear(ptep) do { pte_val(*(ptep)) = 0; } while (0)
307
308 #define pmd_none(pmd) (!pmd_val(pmd))
309 #define pmd_bad(pmd) ((pmd_val(pmd) & ~PAGE_MASK) != 0)
310 #define pmd_present(pmd) ((pmd_val(pmd) & PAGE_MASK) != 0)
311 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
312
313 /*
314 * Permanent address of a page.
315 */
316 #define page_address(page) ((page)->virtual)
317 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
318 #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
319
320 #ifndef __ASSEMBLY__
321 /*
322 * The "pgd_xxx()" functions here are trivial for a folded two-level
323 * setup: the pgd is never bad, and a pmd always exists (as it's folded
324 * into the pgd entry)
325 */
326 extern inline int pgd_none(pgd_t pgd) { return 0; }
327 extern inline int pgd_bad(pgd_t pgd) { return 0; }
328 extern inline int pgd_present(pgd_t pgd) { return 1; }
329 #define pgd_clear(xp) do { } while (0)
330
331 #define pgd_page(pgd) \
332 ((unsigned long) __va(pgd_val(pgd) & PAGE_MASK))
333
334 /*
335 * The following only work if pte_present() is true.
336 * Undefined behaviour if not..
337 */
338 extern inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
339 extern inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
340 extern inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
341 extern inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
342 extern inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
343
344 extern inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
345 extern inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
346
347 extern inline pte_t pte_rdprotect(pte_t pte) {
348 pte_val(pte) &= ~_PAGE_USER; return pte; }
349 extern inline pte_t pte_exprotect(pte_t pte) {
350 pte_val(pte) &= ~_PAGE_USER; return pte; }
351 extern inline pte_t pte_wrprotect(pte_t pte) {
352 pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
353 extern inline pte_t pte_mkclean(pte_t pte) {
354 pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
355 extern inline pte_t pte_mkold(pte_t pte) {
356 pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
357
358 extern inline pte_t pte_mkread(pte_t pte) {
359 pte_val(pte) |= _PAGE_USER; return pte; }
360 extern inline pte_t pte_mkexec(pte_t pte) {
361 pte_val(pte) |= _PAGE_USER; return pte; }
362 extern inline pte_t pte_mkwrite(pte_t pte)
363 {
364 pte_val(pte) |= _PAGE_RW;
365 if (pte_val(pte) & _PAGE_DIRTY)
366 pte_val(pte) |= _PAGE_HWWRITE;
367 return pte;
368 }
369 extern inline pte_t pte_mkdirty(pte_t pte)
370 {
371 pte_val(pte) |= _PAGE_DIRTY;
372 if (pte_val(pte) & _PAGE_RW)
373 pte_val(pte) |= _PAGE_HWWRITE;
374 return pte;
375 }
376 extern inline pte_t pte_mkyoung(pte_t pte) {
377 pte_val(pte) |= _PAGE_ACCESSED; return pte; }
378
379 /* Certain architectures need to do special things when pte's
380 * within a page table are directly modified. Thus, the following
381 * hook is made available.
382 */
383 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
384
385 /*
386 * Conversion functions: convert a page and protection to a page entry,
387 * and a page entry and page directory to the page they refer to.
388 */
389
390 extern inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
391 {
392 pte_t pte;
393 pte_val(pte) = physpage | pgprot_val(pgprot);
394 return pte;
395 }
396
397 #define mk_pte(page,pgprot) \
398 ({ \
399 pte_t pte; \
400 pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \
401 pte; \
402 })
403
404 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
405 {
406 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
407 return pte;
408 }
409
410 #define pmd_page(pmd) (pmd_val(pmd))
411
412 /* to find an entry in a kernel page-table-directory */
413 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
414
415 /* to find an entry in a page-table-directory */
416 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
417 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
418
419 /* Find an entry in the second-level page table.. */
420 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
421 {
422 return (pmd_t *) dir;
423 }
424
425 /* Find an entry in the third-level page table.. */
426 extern inline pte_t * pte_offset(pmd_t * dir, unsigned long address)
427 {
428 return (pte_t *) pmd_page(*dir) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
429 }
430
431 extern pgd_t swapper_pg_dir[1024];
432 extern void paging_init(void);
433
434 /*
435 * Page tables may have changed. We don't need to do anything here
436 * as entries are faulted into the hash table by the low-level
437 * data/instruction access exception handlers.
438 */
439 #define update_mmu_cache(vma, addr, pte) do { } while (0)
440
441 /*
442 * When flushing the tlb entry for a page, we also need to flush the
443 * hash table entry. flush_hash_page is assembler (for speed) in head.S.
444 */
445 extern void flush_hash_segments(unsigned low_vsid, unsigned high_vsid);
446 extern void flush_hash_page(unsigned context, unsigned long va);
447
448 /* Encode and de-code a swap entry */
449 #define SWP_TYPE(entry) (((entry).val >> 1) & 0x3f)
450 #define SWP_OFFSET(entry) ((entry).val >> 8)
451 #define SWP_ENTRY(type, offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
452 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
453 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
454
455 /* CONFIG_APUS */
456 /* For virtual address to physical address conversion */
457 extern void cache_clear(__u32 addr, int length);
458 extern void cache_push(__u32 addr, int length);
459 extern int mm_end_of_chunk (unsigned long addr, int len);
460 extern unsigned long iopa(unsigned long addr);
461 extern unsigned long mm_ptov(unsigned long addr) __attribute__ ((const));
462
463 /* Values for nocacheflag and cmode */
464 /* These are not used by the APUS kernel_map, but prevents
465 compilation errors. */
466 #define KERNELMAP_FULL_CACHING 0
467 #define KERNELMAP_NOCACHE_SER 1
468 #define KERNELMAP_NOCACHE_NONSER 2
469 #define KERNELMAP_NO_COPYBACK 3
470
471 /*
472 * Map some physical address range into the kernel address space.
473 */
474 extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
475 int nocacheflag, unsigned long *memavailp );
476
477 /*
478 * Set cache mode of (kernel space) address range.
479 */
480 extern void kernel_set_cachemode (unsigned long address, unsigned long size,
481 unsigned int cmode);
482
483 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
484 #define PageSkip(page) (0)
485 #define kern_addr_valid(addr) (1)
486
487 #define io_remap_page_range remap_page_range
488
489 #include <asm-generic/pgtable.h>
490
491 #endif __ASSEMBLY__
492 #endif /* _PPC_PGTABLE_H */
493 #endif /* __KERNEL__ */
494
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.