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Linux Cross Reference
Linux/include/asm-sh/irq.h

Version: ~ [ 2.4.0 ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

  1 #ifndef __ASM_SH_IRQ_H
  2 #define __ASM_SH_IRQ_H
  3 
  4 /*
  5  *
  6  * linux/include/asm-sh/irq.h
  7  *
  8  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
  9  * Copyright (C) 2000  Kazumoto Kojima
 10  *
 11  */
 12 
 13 #include <linux/config.h>
 14 #include <asm/machvec.h>
 15 
 16 #if defined(__sh3__)
 17 #define INTC_IPRA       0xfffffee2UL
 18 #define INTC_IPRB       0xfffffee4UL
 19 #elif defined(__SH4__)
 20 #define INTC_IPRA       0xffd00004UL
 21 #define INTC_IPRB       0xffd00008UL
 22 #define INTC_IPRC       0xffd0000cUL
 23 #endif
 24 
 25 #define TIMER_IRQ       16
 26 #define TIMER_IPR_ADDR  INTC_IPRA
 27 #define TIMER_IPR_POS    3
 28 #define TIMER_PRIORITY   2
 29 
 30 #define RTC_IRQ         22
 31 #define RTC_IPR_ADDR    INTC_IPRA
 32 #define RTC_IPR_POS      0
 33 #define RTC_PRIORITY    TIMER_PRIORITY
 34 
 35 #define SCI_ERI_IRQ     23
 36 #define SCI_RXI_IRQ     24
 37 #define SCI_TXI_IRQ     25
 38 #define SCI_IPR_ADDR    INTC_IPRB
 39 #define SCI_IPR_POS     1
 40 #define SCI_PRIORITY    3
 41 
 42 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 43 #define SCIF_ERI_IRQ    56
 44 #define SCIF_RXI_IRQ    57
 45 #define SCIF_BRI_IRQ    58
 46 #define SCIF_TXI_IRQ    59
 47 #define SCIF_IPR_ADDR   INTC_IPRE
 48 #define SCIF_IPR_POS    1
 49 #define SCIF_PRIORITY   3
 50 
 51 #define IRDA_ERI_IRQ    52
 52 #define IRDA_RXI_IRQ    53
 53 #define IRDA_BRI_IRQ    54
 54 #define IRDA_TXI_IRQ    55
 55 #define IRDA_IPR_ADDR   INTC_IPRE
 56 #define IRDA_IPR_POS    2
 57 #define IRDA_PRIORITY   3
 58 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)
 59 #define SCIF_ERI_IRQ    40
 60 #define SCIF_RXI_IRQ    41
 61 #define SCIF_BRI_IRQ    42
 62 #define SCIF_TXI_IRQ    43
 63 #define SCIF_IPR_ADDR   INTC_IPRC
 64 #define SCIF_IPR_POS    1
 65 #define SCIF_PRIORITY   3
 66 #endif
 67 
 68 #ifdef CONFIG_SH_GENERIC
 69 /* In a generic kernel, NR_IRQS is an upper bound, and we should use
 70  * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value.
 71  */
 72 #define NR_IRQS 80
 73 #define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs)
 74 #else
 75 #if defined(__SH4__)
 76 /*
 77  * 48 = 32+16
 78  *
 79  * 32 for on chip support modules.
 80  * 16 for external interrupts.
 81  *
 82  */
 83 #define NR_IRQS 48
 84 #elif defined(CONFIG_CPU_SUBTYPE_SH7707)
 85 #define NR_IRQS 64
 86 #elif defined(CONFIG_CPU_SUBTYPE_SH7708)
 87 #define NR_IRQS 32
 88 #elif defined(CONFIG_CPU_SUBTYPE_SH7709)
 89 #ifdef CONFIG_HD64461
 90 #define NR_IRQS 80              /* HD64461_IRQBASE+16, see hd64461.h */
 91 #else
 92 #define NR_IRQS 61
 93 #endif
 94 #endif
 95 #define ACTUAL_NR_IRQS NR_IRQS
 96 #endif
 97 
 98 extern void disable_irq(unsigned int);
 99 extern void disable_irq_nosync(unsigned int);
100 extern void enable_irq(unsigned int);
101 
102 /*
103  * Function for "on chip support modules".
104  */
105 extern void make_ipr_irq(unsigned int irq, unsigned int addr,
106                          int pos,  int priority);
107 extern void make_imask_irq(unsigned int irq);
108 
109 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
110 #define INTC_IRR0       0xa4000004UL
111 #define INTC_IRR1       0xa4000006UL
112 #define INTC_IRR2       0xa4000008UL
113 
114 #define INTC_ICR0       0xfffffee0UL
115 #define INTC_ICR1       0xa4000010UL
116 #define INTC_ICR2       0xa4000012UL
117 #define INTC_INTER      0xa4000014UL
118 
119 #define INTC_IPRC       0xa4000016UL
120 #define INTC_IPRD       0xa4000018UL
121 #define INTC_IPRE       0xa400001aUL
122 #if defined(CONFIG_CPU_SUBTYPE_SH7707)
123 #define INTC_IPRF       0xa400001cUL
124 #endif
125 
126 #define IRQ0_IRQ        32
127 #define IRQ1_IRQ        33
128 #define IRQ2_IRQ        34
129 #define IRQ3_IRQ        35
130 #define IRQ4_IRQ        36
131 #define IRQ5_IRQ        37
132 
133 #define IRQ0_IRP_ADDR   INTC_IPRC
134 #define IRQ1_IRP_ADDR   INTC_IPRC
135 #define IRQ2_IRP_ADDR   INTC_IPRC
136 #define IRQ3_IRP_ADDR   INTC_IPRC
137 #define IRQ4_IRP_ADDR   INTC_IPRD
138 #define IRQ5_IRP_ADDR   INTC_IPRD
139 
140 #define IRQ0_IRP_POS    0
141 #define IRQ1_IRP_POS    1
142 #define IRQ2_IRP_POS    2
143 #define IRQ3_IRP_POS    3
144 #define IRQ4_IRP_POS    0
145 #define IRQ5_IRP_POS    1
146 
147 #define IRQ0_PRIORITY   1
148 #define IRQ1_PRIORITY   1
149 #define IRQ2_PRIORITY   1
150 #define IRQ3_PRIORITY   1
151 #define IRQ4_PRIORITY   1
152 #define IRQ5_PRIORITY   1
153 #endif
154 
155 extern int hd64461_irq_demux(int irq);
156 
157 #ifdef CONFIG_SH_GENERIC
158 extern __inline__ int irq_demux(int irq) {
159         if (sh_mv.mv_irq_demux) {
160                 irq = sh_mv.mv_irq_demux(irq);
161         }
162         return irq;
163 }
164 #elif defined(CONFIG_HD64461)
165 #define irq_demux(irq) hd64461_irq_demux(irq)
166 #else
167 #define irq_demux(irq) irq
168 #endif
169 
170 #endif /* __ASM_SH_IRQ_H */
171 

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