1 /*
2 * Copyright (C) 1999 Niibe Yutaka
3 *
4 * ASID handling idea taken from MIPS implementation.
5 */
6 #ifndef __ASM_SH_MMU_CONTEXT_H
7 #define __ASM_SH_MMU_CONTEXT_H
8
9 /* The MMU "context" consists of two things:
10 (a) TLB cache version (or round, cycle whatever expression you like)
11 (b) ASID (Address Space IDentifier)
12 */
13
14 /*
15 * Cache of MMU context last used.
16 */
17 extern unsigned long mmu_context_cache;
18
19 #define MMU_CONTEXT_ASID_MASK 0x000000ff
20 #define MMU_CONTEXT_VERSION_MASK 0xffffff00
21 #define MMU_CONTEXT_FIRST_VERSION 0x00000100
22 #define NO_CONTEXT 0
23
24 /* ASID is 8-bit value, so it can't be 0x100 */
25 #define MMU_NO_ASID 0x100
26
27 /*
28 * Virtual Page Number mask
29 */
30 #define MMU_VPN_MASK 0xfffff000
31
32 extern __inline__ void
33 get_new_mmu_context(struct mm_struct *mm)
34 {
35 extern void flush_tlb_all(void);
36
37 unsigned long mc = ++mmu_context_cache;
38
39 if (!(mc & MMU_CONTEXT_ASID_MASK)) {
40 /* We exhaust ASID of this version.
41 Flush all TLB and start new cycle. */
42 flush_tlb_all();
43 /* Fix version if needed.
44 Note that we avoid version #0 to distingush NO_CONTEXT. */
45 if (!mc)
46 mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
47 }
48 mm->context = mc;
49 }
50
51 /*
52 * Get MMU context if needed.
53 */
54 extern __inline__ void
55 get_mmu_context(struct mm_struct *mm)
56 {
57 if (mm) {
58 unsigned long mc = mmu_context_cache;
59 /* Check if we have old version of context.
60 If it's old, we need to get new context with new version. */
61 if ((mm->context ^ mc) & MMU_CONTEXT_VERSION_MASK)
62 get_new_mmu_context(mm);
63 }
64 }
65
66 /*
67 * Initialize the context related info for a new mm_struct
68 * instance.
69 */
70 extern __inline__ int init_new_context(struct task_struct *tsk,
71 struct mm_struct *mm)
72 {
73 mm->context = NO_CONTEXT;
74 return 0;
75 }
76
77 /*
78 * Destroy context related info for an mm_struct that is about
79 * to be put to rest.
80 */
81 extern __inline__ void destroy_context(struct mm_struct *mm)
82 {
83 /* Do nothing */
84 }
85
86 /* Other MMU related constants. */
87
88 #if defined(__sh3__)
89 #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
90 #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
91 #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
92 #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
93
94 #define MMUCR 0xFFFFFFE0 /* MMU Control Register */
95
96 #define MMU_TLB_ADDRESS_ARRAY 0xF2000000
97 #define MMU_PAGE_ASSOC_BIT 0x80
98
99 #define MMU_NTLB_ENTRIES 128 /* for 7708 */
100 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
101
102 #elif defined(__SH4__)
103 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
104 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
105 #define MMU_TTB 0xFF000008 /* Translation table base register */
106 #define MMU_TEA 0xFF00000C /* TLB Exception Address */
107 #define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
108
109 #define MMUCR 0xFF000010 /* MMU Control Register */
110
111 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
112 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
113 #define MMU_PAGE_ASSOC_BIT 0x80
114
115 #define MMU_NTLB_ENTRIES 64 /* for 7750 */
116 #define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */
117
118 #define MMU_ITLB_DATA_ARRAY 0xF3000000
119 #define MMU_UTLB_DATA_ARRAY 0xF7000000
120
121 #define MMU_UTLB_ENTRIES 64
122 #define MMU_U_ENTRY_SHIFT 8
123 #define MMU_UTLB_VALID 0x100
124 #define MMU_ITLB_ENTRIES 4
125 #define MMU_I_ENTRY_SHIFT 8
126 #define MMU_ITLB_VALID 0x100
127 #endif
128
129 extern __inline__ void set_asid(unsigned long asid)
130 {
131 unsigned long __dummy;
132
133 __asm__ __volatile__ ("mov.l %2, %0\n\t"
134 "and %3, %0\n\t"
135 "or %1, %0\n\t"
136 "mov.l %0, %2"
137 : "=&r" (__dummy)
138 : "r" (asid), "m" (__m(MMU_PTEH)),
139 "r" (0xffffff00));
140 }
141
142 extern __inline__ unsigned long get_asid(void)
143 {
144 unsigned long asid;
145
146 __asm__ __volatile__ ("mov.l %1, %0"
147 : "=r" (asid)
148 : "m" (__m(MMU_PTEH)));
149 asid &= MMU_CONTEXT_ASID_MASK;
150 return asid;
151 }
152
153 /*
154 * After we have set current->mm to a new value, this activates
155 * the context for the new mm so we see the new mappings.
156 */
157 extern __inline__ void activate_context(struct mm_struct *mm)
158 {
159 get_mmu_context(mm);
160 set_asid(mm->context & MMU_CONTEXT_ASID_MASK);
161 }
162
163 /* MMU_TTB can be used for optimizing the fault handling.
164 (Currently not used) */
165 extern __inline__ void switch_mm(struct mm_struct *prev,
166 struct mm_struct *next,
167 struct task_struct *tsk, unsigned int cpu)
168 {
169 if (prev != next) {
170 unsigned long __pgdir = (unsigned long)next->pgd;
171
172 clear_bit(cpu, &prev->cpu_vm_mask);
173 set_bit(cpu, &next->cpu_vm_mask);
174 __asm__ __volatile__("mov.l %0, %1"
175 : /* no output */
176 : "r" (__pgdir), "m" (__m(MMU_TTB)));
177 activate_context(next);
178 }
179 }
180
181 #define activate_mm(prev, next) \
182 switch_mm((prev),(next),NULL,smp_processor_id())
183
184 extern __inline__ void
185 enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk, unsigned cpu)
186 {
187 }
188 #endif /* __ASM_SH_MMU_CONTEXT_H */
189
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