1 /* $Id: asi.h,v 1.18 1998/03/09 14:04:46 jj Exp $ */
2 #ifndef _SPARC_ASI_H
3 #define _SPARC_ASI_H
4
5 /* asi.h: Address Space Identifier values for the sparc.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 *
9 * Pioneer work for sun4m: Paul Hatchman (paul@sfe.com.au)
10 * Joint edition for sun4c+sun4m: Pete A. Zaitcev <zaitcev@ipmce.su>
11 */
12
13 /* The first batch are for the sun4c. */
14
15 #define ASI_NULL1 0x00
16 #define ASI_NULL2 0x01
17
18 /* sun4c and sun4 control registers and mmu/vac ops */
19 #define ASI_CONTROL 0x02
20 #define ASI_SEGMAP 0x03
21 #define ASI_PTE 0x04
22 #define ASI_HWFLUSHSEG 0x05
23 #define ASI_HWFLUSHPAGE 0x06
24 #define ASI_REGMAP 0x06
25 #define ASI_HWFLUSHCONTEXT 0x07
26
27 #define ASI_USERTXT 0x08
28 #define ASI_KERNELTXT 0x09
29 #define ASI_USERDATA 0x0a
30 #define ASI_KERNELDATA 0x0b
31
32 /* VAC Cache flushing on sun4c and sun4 */
33 #define ASI_FLUSHSEG 0x0c
34 #define ASI_FLUSHPG 0x0d
35 #define ASI_FLUSHCTX 0x0e
36
37 /* SPARCstation-5: only 6 bits are decoded. */
38 /* wo = Write Only, rw = Read Write; */
39 /* ss = Single Size, as = All Sizes; */
40 #define ASI_M_RES00 0x00 /* Don't touch... */
41 #define ASI_M_UNA01 0x01 /* Same here... */
42 #define ASI_M_MXCC 0x02 /* Access to TI VIKING MXCC registers */
43 #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
44 #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
45 #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
46 #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
47 #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
48 #define ASI_M_USERTXT 0x08 /* Same as ASI_USERTXT; rw, as */
49 #define ASI_M_KERNELTXT 0x09 /* Same as ASI_KERNELTXT; rw, as */
50 #define ASI_M_USERDATA 0x0A /* Same as ASI_USERDATA; rw, as */
51 #define ASI_M_KERNELDATA 0x0B /* Same as ASI_KERNELDATA; rw, as */
52 #define ASI_M_TXTC_TAG 0x0C /* Instruction Cache Tag; rw, ss */
53 #define ASI_M_TXTC_DATA 0x0D /* Instruction Cache Data; rw, ss */
54 #define ASI_M_DATAC_TAG 0x0E /* Data Cache Tag; rw, ss */
55 #define ASI_M_DATAC_DATA 0x0F /* Data Cache Data; rw, ss */
56
57 /* The following cache flushing ASIs work only with the 'sta'
58 * instruction. Results are unpredictable for 'swap' and 'ldstuba',
59 * so don't do it.
60 */
61
62 /* These ASI flushes affect external caches too. */
63 #define ASI_M_FLUSH_PAGE 0x10 /* Flush I&D Cache Line (page); wo, ss */
64 #define ASI_M_FLUSH_SEG 0x11 /* Flush I&D Cache Line (seg); wo, ss */
65 #define ASI_M_FLUSH_REGION 0x12 /* Flush I&D Cache Line (region); wo, ss */
66 #define ASI_M_FLUSH_CTX 0x13 /* Flush I&D Cache Line (context); wo, ss */
67 #define ASI_M_FLUSH_USER 0x14 /* Flush I&D Cache Line (user); wo, ss */
68
69 /* Block-copy operations are available only on certain V8 cpus. */
70 #define ASI_M_BCOPY 0x17 /* Block copy */
71
72 /* These affect only the ICACHE and are Ross HyperSparc and TurboSparc specific. */
73 #define ASI_M_IFLUSH_PAGE 0x18 /* Flush I Cache Line (page); wo, ss */
74 #define ASI_M_IFLUSH_SEG 0x19 /* Flush I Cache Line (seg); wo, ss */
75 #define ASI_M_IFLUSH_REGION 0x1A /* Flush I Cache Line (region); wo, ss */
76 #define ASI_M_IFLUSH_CTX 0x1B /* Flush I Cache Line (context); wo, ss */
77 #define ASI_M_IFLUSH_USER 0x1C /* Flush I Cache Line (user); wo, ss */
78
79 /* Block-fill operations are available on certain V8 cpus */
80 #define ASI_M_BFILL 0x1F
81
82 /* This allows direct access to main memory, actually 0x20 to 0x2f are
83 * the available ASI's for physical ram pass-through, but I don't have
84 * any idea what the other ones do....
85 */
86
87 #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
88 #define ASI_M_FBMEM 0x29 /* Graphics card frame buffer access */
89 #define ASI_M_VMEUS 0x2A /* VME user 16-bit access */
90 #define ASI_M_VMEPS 0x2B /* VME priv 16-bit access */
91 #define ASI_M_VMEUT 0x2C /* VME user 32-bit access */
92 #define ASI_M_VMEPT 0x2D /* VME priv 32-bit access */
93 #define ASI_M_SBUS 0x2E /* Direct SBus access */
94 #define ASI_M_CTL 0x2F /* Control Space (ECC and MXCC are here) */
95
96
97 /* This is ROSS HyperSparc only. */
98 #define ASI_M_FLUSH_IWHOLE 0x31 /* Flush entire ICACHE; wo, ss */
99
100 /* Tsunami/Viking/TurboSparc i/d cache flash clear. */
101 #define ASI_M_IC_FLCLEAR 0x36
102 #define ASI_M_DC_FLCLEAR 0x37
103
104 #define ASI_M_DCDR 0x39 /* Data Cache Diagnostics Register rw, ss */
105
106 #define ASI_M_VIKING_TMP1 0x40 /* Emulation temporary 1 on Viking */
107 #define ASI_M_VIKING_TMP2 0x41 /* Emulation temporary 2 on Viking */
108
109 #define ASI_M_ACTION 0x4c /* Breakpoint Action Register (GNU/Viking) */
110
111 #endif /* _SPARC_ASI_H */
112
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