1 /* $Id: dma.h,v 1.35 1999/12/27 06:37:09 anton Exp $
2 * include/asm-sparc/dma.h
3 *
4 * Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
5 */
6
7 #ifndef _ASM_SPARC_DMA_H
8 #define _ASM_SPARC_DMA_H
9
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13
14 #include <asm/vac-ops.h> /* for invalidate's, etc. */
15 #include <asm/sbus.h>
16 #include <asm/delay.h>
17 #include <asm/oplib.h>
18 #include <asm/system.h>
19 #include <asm/io.h>
20 #include <linux/spinlock.h>
21
22 extern spinlock_t dma_spin_lock;
23
24 static __inline__ unsigned long claim_dma_lock(void)
25 {
26 unsigned long flags;
27 spin_lock_irqsave(&dma_spin_lock, flags);
28 return flags;
29 }
30
31 static __inline__ void release_dma_lock(unsigned long flags)
32 {
33 spin_unlock_irqrestore(&dma_spin_lock, flags);
34 }
35
36 /* These are irrelevant for Sparc DMA, but we leave it in so that
37 * things can compile.
38 */
39 #define MAX_DMA_CHANNELS 8
40 #define MAX_DMA_ADDRESS (~0UL)
41 #define DMA_MODE_READ 1
42 #define DMA_MODE_WRITE 2
43
44 /* Useful constants */
45 #define SIZE_16MB (16*1024*1024)
46 #define SIZE_64K (64*1024)
47
48 /* SBUS DMA controller reg offsets */
49 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
50 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
51 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
52 #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
53
54 /* DVMA chip revisions */
55 enum dvma_rev {
56 dvmarev0,
57 dvmaesc1,
58 dvmarev1,
59 dvmarev2,
60 dvmarev3,
61 dvmarevplus,
62 dvmahme
63 };
64
65 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
66
67 /* Linux DMA information structure, filled during probe. */
68 struct sbus_dma {
69 struct sbus_dma *next;
70 struct sbus_dev *sdev;
71 unsigned long regs;
72
73 /* Status, misc info */
74 int node; /* Prom node for this DMA device */
75 int running; /* Are we doing DMA now? */
76 int allocated; /* Are we "owned" by anyone yet? */
77
78 /* Transfer information. */
79 unsigned long addr; /* Start address of current transfer */
80 int nbytes; /* Size of current transfer */
81 int realbytes; /* For splitting up large transfers, etc. */
82
83 /* DMA revision */
84 enum dvma_rev revision;
85 };
86
87 extern struct sbus_dma *dma_chain;
88
89 /* Broken hardware... */
90 #ifdef CONFIG_SUN4
91 /* Have to sort this out. Does rev0 work fine on sun4[cmd] without isbroken?
92 * Or is rev0 present only on sun4 boxes? -jj */
93 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev0 || (dma)->revision == dvmarev1)
94 #else
95 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
96 #endif
97 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
98
99 /* Main routines in dma.c */
100 extern void dvma_init(struct sbus_bus *);
101
102 /* Fields in the cond_reg register */
103 /* First, the version identification bits */
104 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
105 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
106 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
107 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
108 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
109 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
110 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
111
112 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
113 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
114 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
115 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
116 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
117 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
118 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
119 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
120 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
121 #define DMA_RST_BPP DMA_RST_SCSI /* Reset the BPP controller */
122 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
123 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
124 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
125 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
126 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
127 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
128 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
129 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
130 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
131 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
132 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
133 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
134 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
135 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
136 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
137 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
138 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
139 #define DMA_BRST64 0x00080000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
140 #define DMA_BRST32 0x00040000 /* SCSI/BPP: 32byte bursts */
141 #define DMA_BRST16 0x00000000 /* SCSI/BPP: 16byte bursts */
142 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
143 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
144 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
145 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
146 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
147 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
148 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
149 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
150 #define DMA_BPP_ON DMA_SCSI_ON /* Enable BPP dma */
151 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
152 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
153 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
154 #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
155
156 /* Values describing the burst-size property from the PROM */
157 #define DMA_BURST1 0x01
158 #define DMA_BURST2 0x02
159 #define DMA_BURST4 0x04
160 #define DMA_BURST8 0x08
161 #define DMA_BURST16 0x10
162 #define DMA_BURST32 0x20
163 #define DMA_BURST64 0x40
164 #define DMA_BURSTBITS 0x7f
165
166 /* Determine highest possible final transfer address given a base */
167 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
168
169 /* Yes, I hack a lot of elisp in my spare time... */
170 #define DMA_ERROR_P(regs) ((((regs)->cond_reg) & DMA_HNDL_ERROR))
171 #define DMA_IRQ_P(regs) ((((regs)->cond_reg) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
172 #define DMA_WRITE_P(regs) ((((regs)->cond_reg) & DMA_ST_WRITE))
173 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
174 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))
175 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))
176 #define DMA_PUNTFIFO(regs) ((((regs)->cond_reg) |= DMA_FIFO_INV))
177 #define DMA_SETSTART(regs, addr) ((((regs)->st_addr) = (char *) addr))
178 #define DMA_BEGINDMA_W(regs) \
179 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
180 #define DMA_BEGINDMA_R(regs) \
181 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
182
183 /* For certain DMA chips, we need to disable ints upon irq entry
184 * and turn them back on when we are done. So in any ESP interrupt
185 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
186 * when leaving the handler. You have been warned...
187 */
188 #define DMA_IRQ_ENTRY(dma, dregs) do { \
189 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
190 } while (0)
191
192 #define DMA_IRQ_EXIT(dma, dregs) do { \
193 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
194 } while(0)
195
196 #if 0 /* P3 this stuff is inline in ledma.c:init_restart_ledma() */
197 /* Pause until counter runs out or BIT isn't set in the DMA condition
198 * register.
199 */
200 extern __inline__ void sparc_dma_pause(struct sparc_dma_registers *regs,
201 unsigned long bit)
202 {
203 int ctr = 50000; /* Let's find some bugs ;) */
204
205 /* Busy wait until the bit is not set any more */
206 while((regs->cond_reg&bit) && (ctr>0)) {
207 ctr--;
208 __delay(5);
209 }
210
211 /* Check for bogus outcome. */
212 if(!ctr)
213 panic("DMA timeout");
214 }
215
216 /* Reset the friggin' thing... */
217 #define DMA_RESET(dma) do { \
218 struct sparc_dma_registers *regs = dma->regs; \
219 /* Let the current FIFO drain itself */ \
220 sparc_dma_pause(regs, (DMA_FIFO_ISDRAIN)); \
221 /* Reset the logic */ \
222 regs->cond_reg |= (DMA_RST_SCSI); /* assert */ \
223 __delay(400); /* let the bits set ;) */ \
224 regs->cond_reg &= ~(DMA_RST_SCSI); /* de-assert */ \
225 sparc_dma_enable_interrupts(regs); /* Re-enable interrupts */ \
226 /* Enable FAST transfers if available */ \
227 if(dma->revision>dvmarev1) regs->cond_reg |= DMA_3CLKS; \
228 dma->running = 0; \
229 } while(0)
230 #endif
231
232 #define for_each_dvma(dma) \
233 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
234
235 extern int get_dma_list(char *);
236 extern int request_dma(unsigned int, __const__ char *);
237 extern void free_dma(unsigned int);
238
239 /* From PCI */
240
241 #ifdef CONFIG_PCI
242 extern int isa_dma_bridge_buggy;
243 #else
244 #define isa_dma_bridge_buggy (0)
245 #endif
246
247 #endif /* !(_ASM_SPARC_DMA_H) */
248
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