1 /* $Id: ecc.h,v 1.3 1996/04/25 06:12:57 davem Exp $
2 * ecc.h: Definitions and defines for the external cache/memory
3 * controller on the sun4m.
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8 #ifndef _SPARC_ECC_H
9 #define _SPARC_ECC_H
10
11 /* These registers are accessed through the SRMMU passthrough ASI 0x20 */
12 #define ECC_ENABLE 0x00000000 /* ECC enable register */
13 #define ECC_FSTATUS 0x00000008 /* ECC fault status register */
14 #define ECC_FADDR 0x00000010 /* ECC fault address register */
15 #define ECC_DIGNOSTIC 0x00000018 /* ECC diagnostics register */
16 #define ECC_MBAENAB 0x00000020 /* MBus arbiter enable register */
17 #define ECC_DMESG 0x00001000 /* Diagnostic message passing area */
18
19 /* ECC MBus Arbiter Enable register:
20 *
21 * ----------------------------------------
22 * | |SBUS|MOD3|MOD2|MOD1|RSV|
23 * ----------------------------------------
24 * 31 5 4 3 2 1 0
25 *
26 * SBUS: Enable MBus Arbiter on the SBus 0=off 1=on
27 * MOD3: Enable MBus Arbiter on MBus module 3 0=off 1=on
28 * MOD2: Enable MBus Arbiter on MBus module 2 0=off 1=on
29 * MOD1: Enable MBus Arbiter on MBus module 1 0=off 1=on
30 */
31
32 #define ECC_MBAE_SBUS 0x00000010
33 #define ECC_MBAE_MOD3 0x00000008
34 #define ECC_MBAE_MOD2 0x00000004
35 #define ECC_MBAE_MOD1 0x00000002
36
37 /* ECC Fault Control Register layout:
38 *
39 * -----------------------------
40 * | RESV | ECHECK | EINT |
41 * -----------------------------
42 * 31 2 1 0
43 *
44 * ECHECK: Enable ECC checking. 0=off 1=on
45 * EINT: Enable Interrupts for correctable errors. 0=off 1=on
46 */
47 #define ECC_FCR_CHECK 0x00000002
48 #define ECC_FCR_INTENAB 0x00000001
49
50 /* ECC Fault Address Register Zero layout:
51 *
52 * -----------------------------------------------------
53 * | MID | S | RSV | VA | BM |AT| C| SZ |TYP| PADDR |
54 * -----------------------------------------------------
55 * 31-28 27 26-22 21-14 13 12 11 10-8 7-4 3-0
56 *
57 * MID: ModuleID of the faulting processor. ie. who did it?
58 * S: Supervisor/Privileged access? 0=no 1=yes
59 * VA: Bits 19-12 of the virtual faulting address, these are the
60 * superset bits in the virtual cache and can be used for
61 * a flush operation if necessary.
62 * BM: Boot mode? 0=no 1=yes This is just like the SRMMU boot
63 * mode bit.
64 * AT: Did this fault happen during an atomic instruction? 0=no
65 * 1=yes. This means either an 'ldstub' or 'swap' instruction
66 * was in progress (but not finished) when this fault happened.
67 * This indicated whether the bus was locked when the fault
68 * occurred.
69 * C: Did the pte for this access indicate that it was cacheable?
70 * 0=no 1=yes
71 * SZ: The size of the transaction.
72 * TYP: The transaction type.
73 * PADDR: Bits 35-32 of the physical address for the fault.
74 */
75 #define ECC_FADDR0_MIDMASK 0xf0000000
76 #define ECC_FADDR0_S 0x08000000
77 #define ECC_FADDR0_VADDR 0x003fc000
78 #define ECC_FADDR0_BMODE 0x00002000
79 #define ECC_FADDR0_ATOMIC 0x00001000
80 #define ECC_FADDR0_CACHE 0x00000800
81 #define ECC_FADDR0_SIZE 0x00000700
82 #define ECC_FADDR0_TYPE 0x000000f0
83 #define ECC_FADDR0_PADDR 0x0000000f
84
85 /* ECC Fault Address Register One layout:
86 *
87 * -------------------------------------
88 * | Physical Address 31-0 |
89 * -------------------------------------
90 * 31 0
91 *
92 * You get the upper 4 bits of the physical address from the
93 * PADDR field in ECC Fault Address Zero register.
94 */
95
96 /* ECC Fault Status Register layout:
97 *
98 * ----------------------------------------------
99 * | RESV|C2E|MULT|SYNDROME|DWORD|UNC|TIMEO|BS|C|
100 * ----------------------------------------------
101 * 31-18 17 16 15-8 7-4 3 2 1 0
102 *
103 * C2E: A C2 graphics error occurred. 0=no 1=yes (SS10 only)
104 * MULT: Multiple errors occurred ;-O 0=no 1=prom_panic(yes)
105 * SYNDROME: Controller is mentally unstable.
106 * DWORD:
107 * UNC: Uncorrectable error. 0=no 1=yes
108 * TIMEO: Timeout occurred. 0=no 1=yes
109 * BS: C2 graphics bad slot access. 0=no 1=yes (SS10 only)
110 * C: Correctable error? 0=no 1=yes
111 */
112
113 #define ECC_FSR_C2ERR 0x00020000
114 #define ECC_FSR_MULT 0x00010000
115 #define ECC_FSR_SYND 0x0000ff00
116 #define ECC_FSR_DWORD 0x000000f0
117 #define ECC_FSR_UNC 0x00000008
118 #define ECC_FSR_TIMEO 0x00000004
119 #define ECC_FSR_BADSLOT 0x00000002
120 #define ECC_FSR_C 0x00000001
121
122 #endif /* !(_SPARC_ECC_H) */
123
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