1 /* $Id: sbi.h,v 1.2 1998/03/09 14:04:48 jj Exp $
2 * sbi.h: SBI (Sbus Interface on sun4d) definitions
3 *
4 * Copyright (C) 1997 Jakub Jelinek <jj@sunsite.mff.cuni.cz>
5 */
6
7 #ifndef _SPARC_SBI_H
8 #define _SPARC_SBI_H
9
10 #include <asm/obio.h>
11
12 /* SBI */
13 struct sbi_regs {
14 /* 0x0000 */ u32 cid; /* Component ID */
15 /* 0x0004 */ u32 ctl; /* Control */
16 /* 0x0008 */ u32 status; /* Status */
17 u32 _unused1;
18
19 /* 0x0010 */ u32 cfg0; /* Slot0 config reg */
20 /* 0x0014 */ u32 cfg1; /* Slot1 config reg */
21 /* 0x0018 */ u32 cfg2; /* Slot2 config reg */
22 /* 0x001c */ u32 cfg3; /* Slot3 config reg */
23
24 /* 0x0020 */ u32 stb0; /* Streaming buf control for slot 0 */
25 /* 0x0024 */ u32 stb1; /* Streaming buf control for slot 1 */
26 /* 0x0028 */ u32 stb2; /* Streaming buf control for slot 2 */
27 /* 0x002c */ u32 stb3; /* Streaming buf control for slot 3 */
28
29 /* 0x0030 */ u32 intr_state; /* Interrupt state */
30 /* 0x0034 */ u32 intr_tid; /* Interrupt target ID */
31 /* 0x0038 */ u32 intr_diag; /* Interrupt diagnostics */
32 };
33
34 #define SBI_CID 0x02800000
35 #define SBI_CTL 0x02800004
36 #define SBI_STATUS 0x02800008
37 #define SBI_CFG0 0x02800010
38 #define SBI_CFG1 0x02800014
39 #define SBI_CFG2 0x02800018
40 #define SBI_CFG3 0x0280001c
41 #define SBI_STB0 0x02800020
42 #define SBI_STB1 0x02800024
43 #define SBI_STB2 0x02800028
44 #define SBI_STB3 0x0280002c
45 #define SBI_INTR_STATE 0x02800030
46 #define SBI_INTR_TID 0x02800034
47 #define SBI_INTR_DIAG 0x02800038
48
49 /* Burst bits for 8, 16, 32, 64 are in cfgX registers at bits 2, 3, 4, 5 respectively */
50 #define SBI_CFG_BURST_MASK 0x0000001e
51
52 /* How to make devid from sbi no */
53 #define SBI2DEVID(sbino) ((sbino<<4)|2)
54
55 /* intr_state has 4 bits for slots 0 .. 3 and these bits are repeated for each sbus irq level
56 *
57 * +-------+-------+-------+-------+-------+-------+-------+-------+
58 * SBUS IRQ LEVEL | 7 | 6 | 5 | 4 | 3 | 2 | 1 | |
59 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ Reser |
60 * SLOT # |3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0|3|2|1|0| ved |
61 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-------+
62 * Bits 31 27 23 19 15 11 7 3 0
63 */
64
65
66 #ifndef __ASSEMBLY__
67
68 extern __inline__ int acquire_sbi(int devid, int mask)
69 {
70 __asm__ __volatile__ ("swapa [%2] %3, %0" :
71 "=r" (mask) :
72 "" (mask),
73 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
74 "i" (ASI_M_CTL));
75 return mask;
76 }
77
78 extern __inline__ void release_sbi(int devid, int mask)
79 {
80 __asm__ __volatile__ ("sta %0, [%1] %2" : :
81 "r" (mask),
82 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_STATE),
83 "i" (ASI_M_CTL));
84 }
85
86 extern __inline__ void set_sbi_tid(int devid, int targetid)
87 {
88 __asm__ __volatile__ ("sta %0, [%1] %2" : :
89 "r" (targetid),
90 "r" (ECSR_DEV_BASE(devid) | SBI_INTR_TID),
91 "i" (ASI_M_CTL));
92 }
93
94 extern __inline__ int get_sbi_ctl(int devid, int cfgno)
95 {
96 int cfg;
97
98 __asm__ __volatile__ ("lda [%1] %2, %0" :
99 "=r" (cfg) :
100 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
101 "i" (ASI_M_CTL));
102 return cfg;
103 }
104
105 extern __inline__ void set_sbi_ctl(int devid, int cfgno, int cfg)
106 {
107 __asm__ __volatile__ ("sta %0, [%1] %2" : :
108 "r" (cfg),
109 "r" ((ECSR_DEV_BASE(devid) | SBI_CFG0) + (cfgno<<2)),
110 "i" (ASI_M_CTL));
111 }
112
113 #endif /* !__ASSEMBLY__ */
114
115 #endif /* !(_SPARC_SBI_H) */
116
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