1 /* $Id: tsunami.h,v 1.5 1996/08/29 09:49:03 davem Exp $
2 * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 */
6
7 #ifndef _SPARC_TSUNAMI_H
8 #define _SPARC_TSUNAMI_H
9
10 #include <asm/asi.h>
11
12 /* The MMU control register on the Tsunami:
13 *
14 * -----------------------------------------------------------------------
15 * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
16 * -----------------------------------------------------------------------
17 * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
18 *
19 * SW: Enable Software Table Walks 0=off 1=on
20 * AV: Address View bit
21 * DV: Data View bit
22 * MV: Memory View bit
23 * PC: Parity Control
24 * ITD: ITBR disable
25 * ALC: Alternate Cacheable
26 * PE: Parity Enable 0=off 1=on
27 * RC: Refresh Control
28 * IE: Instruction cache Enable 0=off 1=on
29 * DE: Data cache Enable 0=off 1=on
30 * NF: No Fault, same as all other SRMMUs
31 * ME: MMU Enable, same as all other SRMMUs
32 */
33
34 #define TSUNAMI_SW 0x00800000
35 #define TSUNAMI_AV 0x00400000
36 #define TSUNAMI_DV 0x00200000
37 #define TSUNAMI_MV 0x00100000
38 #define TSUNAMI_PC 0x00020000
39 #define TSUNAMI_ITD 0x00010000
40 #define TSUNAMI_ALC 0x00008000
41 #define TSUNAMI_PE 0x00001000
42 #define TSUNAMI_RCMASK 0x00000C00
43 #define TSUNAMI_IENAB 0x00000200
44 #define TSUNAMI_DENAB 0x00000100
45 #define TSUNAMI_NF 0x00000002
46 #define TSUNAMI_ME 0x00000001
47
48 extern __inline__ void tsunami_flush_icache(void)
49 {
50 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
51 "i" (ASI_M_IC_FLCLEAR) : "memory");
52 }
53
54 extern __inline__ void tsunami_flush_dcache(void)
55 {
56 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
57 "i" (ASI_M_DC_FLCLEAR) : "memory");
58 }
59
60 #endif /* !(_SPARC_TSUNAMI_H) */
61
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