1 /* $Id: dma.h,v 1.19 2000/01/28 13:43:14 jj Exp $
2 * include/asm-sparc64/dma.h
3 *
4 * Copyright 1996 (C) David S. Miller (davem@caip.rutgers.edu)
5 */
6
7 #ifndef _ASM_SPARC64_DMA_H
8 #define _ASM_SPARC64_DMA_H
9
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/types.h>
13 #include <linux/spinlock.h>
14
15 #include <asm/sbus.h>
16 #include <asm/delay.h>
17 #include <asm/oplib.h>
18
19 extern spinlock_t dma_spin_lock;
20
21 #define claim_dma_lock() \
22 ({ unsigned long flags; \
23 spin_lock_irqsave(&dma_spin_lock, flags); \
24 flags; \
25 })
26
27 #define release_dma_lock(__flags) \
28 spin_unlock_irqrestore(&dma_spin_lock, __flags);
29
30 /* These are irrelevant for Sparc DMA, but we leave it in so that
31 * things can compile.
32 */
33 #define MAX_DMA_CHANNELS 8
34 #define DMA_MODE_READ 1
35 #define DMA_MODE_WRITE 2
36 #define MAX_DMA_ADDRESS (~0UL)
37
38 /* Useful constants */
39 #define SIZE_16MB (16*1024*1024)
40 #define SIZE_64K (64*1024)
41
42 /* SBUS DMA controller reg offsets */
43 #define DMA_CSR 0x00UL /* rw DMA control/status register 0x00 */
44 #define DMA_ADDR 0x04UL /* rw DMA transfer address register 0x04 */
45 #define DMA_COUNT 0x08UL /* rw DMA transfer count register 0x08 */
46 #define DMA_TEST 0x0cUL /* rw DMA test/debug register 0x0c */
47
48 /* DVMA chip revisions */
49 enum dvma_rev {
50 dvmarev0,
51 dvmaesc1,
52 dvmarev1,
53 dvmarev2,
54 dvmarev3,
55 dvmarevplus,
56 dvmahme
57 };
58
59 #define DMA_HASCOUNT(rev) ((rev)==dvmaesc1)
60
61 /* Linux DMA information structure, filled during probe. */
62 struct sbus_dma {
63 struct sbus_dma *next;
64 struct sbus_dev *sdev;
65 unsigned long regs;
66
67 /* Status, misc info */
68 int node; /* Prom node for this DMA device */
69 int running; /* Are we doing DMA now? */
70 int allocated; /* Are we "owned" by anyone yet? */
71
72 /* Transfer information. */
73 u32 addr; /* Start address of current transfer */
74 int nbytes; /* Size of current transfer */
75 int realbytes; /* For splitting up large transfers, etc. */
76
77 /* DMA revision */
78 enum dvma_rev revision;
79 };
80
81 extern struct sbus_dma *dma_chain;
82
83 /* Broken hardware... */
84 #define DMA_ISBROKEN(dma) ((dma)->revision == dvmarev1)
85 #define DMA_ISESC1(dma) ((dma)->revision == dvmaesc1)
86
87 /* Main routines in dma.c */
88 extern void dvma_init(struct sbus_bus *);
89
90 /* Fields in the cond_reg register */
91 /* First, the version identification bits */
92 #define DMA_DEVICE_ID 0xf0000000 /* Device identification bits */
93 #define DMA_VERS0 0x00000000 /* Sunray DMA version */
94 #define DMA_ESCV1 0x40000000 /* DMA ESC Version 1 */
95 #define DMA_VERS1 0x80000000 /* DMA rev 1 */
96 #define DMA_VERS2 0xa0000000 /* DMA rev 2 */
97 #define DMA_VERHME 0xb0000000 /* DMA hme gate array */
98 #define DMA_VERSPLUS 0x90000000 /* DMA rev 1 PLUS */
99
100 #define DMA_HNDL_INTR 0x00000001 /* An IRQ needs to be handled */
101 #define DMA_HNDL_ERROR 0x00000002 /* We need to take an error */
102 #define DMA_FIFO_ISDRAIN 0x0000000c /* The DMA FIFO is draining */
103 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */
104 #define DMA_FIFO_INV 0x00000020 /* Invalidate the FIFO */
105 #define DMA_ACC_SZ_ERR 0x00000040 /* The access size was bad */
106 #define DMA_FIFO_STDRAIN 0x00000040 /* DMA_VERS1 Drain the FIFO */
107 #define DMA_RST_SCSI 0x00000080 /* Reset the SCSI controller */
108 #define DMA_RST_ENET DMA_RST_SCSI /* Reset the ENET controller */
109 #define DMA_ST_WRITE 0x00000100 /* write from device to memory */
110 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */
111 #define DMA_PEND_READ 0x00000400 /* DMA_VERS1/0/PLUS Pending Read */
112 #define DMA_ESC_BURST 0x00000800 /* 1=16byte 0=32byte */
113 #define DMA_READ_AHEAD 0x00001800 /* DMA read ahead partial longword */
114 #define DMA_DSBL_RD_DRN 0x00001000 /* No EC drain on slave reads */
115 #define DMA_BCNT_ENAB 0x00002000 /* If on, use the byte counter */
116 #define DMA_TERM_CNTR 0x00004000 /* Terminal counter */
117 #define DMA_SCSI_SBUS64 0x00008000 /* HME: Enable 64-bit SBUS mode. */
118 #define DMA_CSR_DISAB 0x00010000 /* No FIFO drains during csr */
119 #define DMA_SCSI_DISAB 0x00020000 /* No FIFO drains during reg */
120 #define DMA_DSBL_WR_INV 0x00020000 /* No EC inval. on slave writes */
121 #define DMA_ADD_ENABLE 0x00040000 /* Special ESC DVMA optimization */
122 #define DMA_E_BURSTS 0x000c0000 /* ENET: SBUS r/w burst mask */
123 #define DMA_E_BURST32 0x00040000 /* ENET: SBUS 32 byte r/w burst */
124 #define DMA_E_BURST16 0x00000000 /* ENET: SBUS 16 byte r/w burst */
125 #define DMA_BRST_SZ 0x000c0000 /* SCSI: SBUS r/w burst size */
126 #define DMA_BRST64 0x000c0000 /* SCSI: 64byte bursts (HME on UltraSparc only) */
127 #define DMA_BRST32 0x00040000 /* SCSI: 32byte bursts */
128 #define DMA_BRST16 0x00000000 /* SCSI: 16byte bursts */
129 #define DMA_BRST0 0x00080000 /* SCSI: no bursts (non-HME gate arrays) */
130 #define DMA_ADDR_DISAB 0x00100000 /* No FIFO drains during addr */
131 #define DMA_2CLKS 0x00200000 /* Each transfer = 2 clock ticks */
132 #define DMA_3CLKS 0x00400000 /* Each transfer = 3 clock ticks */
133 #define DMA_EN_ENETAUI DMA_3CLKS /* Put lance into AUI-cable mode */
134 #define DMA_CNTR_DISAB 0x00800000 /* No IRQ when DMA_TERM_CNTR set */
135 #define DMA_AUTO_NADDR 0x01000000 /* Use "auto nxt addr" feature */
136 #define DMA_SCSI_ON 0x02000000 /* Enable SCSI dma */
137 #define DMA_PARITY_OFF 0x02000000 /* HME: disable parity checking */
138 #define DMA_LOADED_ADDR 0x04000000 /* Address has been loaded */
139 #define DMA_LOADED_NADDR 0x08000000 /* Next address has been loaded */
140 #define DMA_RESET_FAS366 0x08000000 /* HME: Assert RESET to FAS366 */
141
142 /* Values describing the burst-size property from the PROM */
143 #define DMA_BURST1 0x01
144 #define DMA_BURST2 0x02
145 #define DMA_BURST4 0x04
146 #define DMA_BURST8 0x08
147 #define DMA_BURST16 0x10
148 #define DMA_BURST32 0x20
149 #define DMA_BURST64 0x40
150 #define DMA_BURSTBITS 0x7f
151
152 /* Determine highest possible final transfer address given a base */
153 #define DMA_MAXEND(addr) (0x01000000UL-(((unsigned long)(addr))&0x00ffffffUL))
154
155 /* Yes, I hack a lot of elisp in my spare time... */
156 #define DMA_ERROR_P(regs) (((sbus_readl((regs) + DMA_CSR) & DMA_HNDL_ERROR))
157 #define DMA_IRQ_P(regs) (((sbus_readl((regs) + DMA_CSR)) & (DMA_HNDL_INTR | DMA_HNDL_ERROR)))
158 #define DMA_WRITE_P(regs) (((sbus_readl((regs) + DMA_CSR) & DMA_ST_WRITE))
159 #define DMA_OFF(__regs) \
160 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
161 tmp &= ~DMA_ENABLE; \
162 sbus_writel(tmp, (__regs) + DMA_CSR); \
163 } while(0)
164 #define DMA_INTSOFF(__regs) \
165 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
166 tmp &= ~DMA_INT_ENAB; \
167 sbus_writel(tmp, (__regs) + DMA_CSR); \
168 } while(0)
169 #define DMA_INTSON(__regs) \
170 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
171 tmp |= DMA_INT_ENAB; \
172 sbus_writel(tmp, (__regs) + DMA_CSR); \
173 } while(0)
174 #define DMA_PUNTFIFO(__regs) \
175 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
176 tmp |= DMA_FIFO_INV; \
177 sbus_writel(tmp, (__regs) + DMA_CSR); \
178 } while(0)
179 #define DMA_SETSTART(__regs, __addr) \
180 sbus_writel((u32)(__addr), (__regs) + DMA_ADDR);
181 #define DMA_BEGINDMA_W(__regs) \
182 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
183 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \
184 sbus_writel(tmp, (__regs) + DMA_CSR); \
185 } while(0)
186 #define DMA_BEGINDMA_R(__regs) \
187 do { u32 tmp = sbus_readl((__regs) + DMA_CSR); \
188 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
189 tmp &= ~DMA_ST_WRITE; \
190 sbus_writel(tmp, (__regs) + DMA_CSR); \
191 } while(0)
192
193 /* For certain DMA chips, we need to disable ints upon irq entry
194 * and turn them back on when we are done. So in any ESP interrupt
195 * handler you *must* call DMA_IRQ_ENTRY upon entry and DMA_IRQ_EXIT
196 * when leaving the handler. You have been warned...
197 */
198 #define DMA_IRQ_ENTRY(dma, dregs) do { \
199 if(DMA_ISBROKEN(dma)) DMA_INTSOFF(dregs); \
200 } while (0)
201
202 #define DMA_IRQ_EXIT(dma, dregs) do { \
203 if(DMA_ISBROKEN(dma)) DMA_INTSON(dregs); \
204 } while(0)
205
206 #define for_each_dvma(dma) \
207 for((dma) = dma_chain; (dma); (dma) = (dma)->next)
208
209 extern int get_dma_list(char *);
210 extern int request_dma(unsigned int, __const__ char *);
211 extern void free_dma(unsigned int);
212
213 /* From PCI */
214
215 #ifdef CONFIG_PCI
216 extern int isa_dma_bridge_buggy;
217 #else
218 #define isa_dma_bridge_buggy (0)
219 #endif
220
221 /* We support dynamic DMA remapping and adjacent SG entries
222 * which have addresses modulo DMA_CHUNK_SIZE will be merged
223 * by dma_prepare_sg().
224 */
225 #define DMA_CHUNK_SIZE 8192
226
227 #endif /* !(_ASM_SPARC64_DMA_H) */
228
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