1 /* $Id: pgtable.h,v 1.135 2000/11/08 04:49:24 davem Exp $
2 * pgtable.h: SpitFire page table operations.
3 *
4 * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #ifndef _SPARC64_PGTABLE_H
9 #define _SPARC64_PGTABLE_H
10
11 /* This file contains the functions and defines necessary to modify and use
12 * the SpitFire page tables.
13 */
14
15 #include <asm/spitfire.h>
16 #include <asm/asi.h>
17 #include <asm/mmu_context.h>
18 #include <asm/system.h>
19
20 #ifndef __ASSEMBLY__
21
22 #define PG_dcache_dirty PG_arch_1
23
24 /* Certain architectures need to do special things when pte's
25 * within a page table are directly modified. Thus, the following
26 * hook is made available.
27 */
28 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
29
30 /* PMD_SHIFT determines the size of the area a second-level page table can map */
31 #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3))
32 #define PMD_SIZE (1UL << PMD_SHIFT)
33 #define PMD_MASK (~(PMD_SIZE-1))
34
35 /* PGDIR_SHIFT determines what a third-level page table entry can map */
36 #define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3) + (PAGE_SHIFT-2))
37 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
38 #define PGDIR_MASK (~(PGDIR_SIZE-1))
39
40 /* Entries per page directory level. */
41 #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3))
42
43 /* We the first one in this file, what we export to the kernel
44 * is different so we can optimize correctly for 32-bit tasks.
45 */
46 #define REAL_PTRS_PER_PMD (1UL << (PAGE_SHIFT-2))
47 #define PTRS_PER_PMD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
48 (REAL_PTRS_PER_PMD >> 2) : (REAL_PTRS_PER_PMD)))
49
50 /* We cannot use the top 16G because VPTE table lives there. */
51 #define PTRS_PER_PGD ((1UL << (PAGE_SHIFT-3))-1)
52
53 /* Kernel has a separate 44bit address space. */
54 #define USER_PTRS_PER_PGD ((const int)((current->thread.flags & SPARC_FLAG_32BIT) ? \
55 (1) : (PTRS_PER_PGD)))
56 #define FIRST_USER_PGD_NR 0
57
58 #define PTE_TABLE_SIZE 0x2000 /* 1024 entries 8 bytes each */
59 #define PMD_TABLE_SIZE 0x2000 /* 2048 entries 4 bytes each */
60 #define PGD_TABLE_SIZE 0x1000 /* 1024 entries 4 bytes each */
61
62 /* NOTE: TLB miss handlers depend heavily upon where this is. */
63 #define VMALLOC_START 0x0000000140000000UL
64 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
65 #define VMALLOC_END 0x0000000200000000UL
66
67 #define pte_ERROR(e) __builtin_trap()
68 #define pmd_ERROR(e) __builtin_trap()
69 #define pgd_ERROR(e) __builtin_trap()
70
71 #endif /* !(__ASSEMBLY__) */
72
73 /* SpitFire TTE bits. */
74 #define _PAGE_VALID 0x8000000000000000 /* Valid TTE */
75 #define _PAGE_R 0x8000000000000000 /* Used to keep ref bit up to date */
76 #define _PAGE_SZ4MB 0x6000000000000000 /* 4MB Page */
77 #define _PAGE_SZ512K 0x4000000000000000 /* 512K Page */
78 #define _PAGE_SZ64K 0x2000000000000000 /* 64K Page */
79 #define _PAGE_SZ8K 0x0000000000000000 /* 8K Page */
80 #define _PAGE_NFO 0x1000000000000000 /* No Fault Only */
81 #define _PAGE_IE 0x0800000000000000 /* Invert Endianness */
82 #define _PAGE_SOFT2 0x07FC000000000000 /* Second set of software bits */
83 #define _PAGE_DIAG 0x0003FE0000000000 /* Diagnostic TTE bits */
84 #define _PAGE_PADDR 0x000001FFFFFFE000 /* Physical Address bits [40:13] */
85 #define _PAGE_SOFT 0x0000000000001F80 /* First set of software bits */
86 #define _PAGE_L 0x0000000000000040 /* Locked TTE */
87 #define _PAGE_CP 0x0000000000000020 /* Cacheable in Physical Cache */
88 #define _PAGE_CV 0x0000000000000010 /* Cacheable in Virtual Cache */
89 #define _PAGE_E 0x0000000000000008 /* side-Effect */
90 #define _PAGE_P 0x0000000000000004 /* Privileged Page */
91 #define _PAGE_W 0x0000000000000002 /* Writable */
92 #define _PAGE_G 0x0000000000000001 /* Global */
93
94 /* Here are the SpitFire software bits we use in the TTE's. */
95 #define _PAGE_MODIFIED 0x0000000000000800 /* Modified Page (ie. dirty) */
96 #define _PAGE_ACCESSED 0x0000000000000400 /* Accessed Page (ie. referenced) */
97 #define _PAGE_READ 0x0000000000000200 /* Readable SW Bit */
98 #define _PAGE_WRITE 0x0000000000000100 /* Writable SW Bit */
99 #define _PAGE_PRESENT 0x0000000000000080 /* Present Page (ie. not swapped out) */
100
101 #define _PAGE_CACHE (_PAGE_CP | _PAGE_CV)
102
103 #define __DIRTY_BITS (_PAGE_MODIFIED | _PAGE_WRITE | _PAGE_W)
104 #define __ACCESS_BITS (_PAGE_ACCESSED | _PAGE_READ | _PAGE_R)
105 #define __PRIV_BITS _PAGE_P
106
107 #define PAGE_NONE __pgprot (_PAGE_PRESENT | _PAGE_ACCESSED)
108
109 /* Don't set the TTE _PAGE_W bit here, else the dirty bit never gets set. */
110 #define PAGE_SHARED __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
111 __ACCESS_BITS | _PAGE_WRITE)
112
113 #define PAGE_COPY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
114 __ACCESS_BITS)
115
116 #define PAGE_READONLY __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
117 __ACCESS_BITS)
118
119 #define PAGE_KERNEL __pgprot (_PAGE_PRESENT | _PAGE_VALID | _PAGE_CACHE | \
120 __PRIV_BITS | __ACCESS_BITS | __DIRTY_BITS)
121
122 #define PAGE_INVALID __pgprot (0)
123
124 #define _PFN_MASK _PAGE_PADDR
125
126 #define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_MODIFIED | _PAGE_ACCESSED | _PAGE_PRESENT)
127
128 #define pg_iobits (_PAGE_VALID | _PAGE_PRESENT | __DIRTY_BITS | __ACCESS_BITS | _PAGE_E)
129
130 #define __P000 PAGE_NONE
131 #define __P001 PAGE_READONLY
132 #define __P010 PAGE_COPY
133 #define __P011 PAGE_COPY
134 #define __P100 PAGE_READONLY
135 #define __P101 PAGE_READONLY
136 #define __P110 PAGE_COPY
137 #define __P111 PAGE_COPY
138
139 #define __S000 PAGE_NONE
140 #define __S001 PAGE_READONLY
141 #define __S010 PAGE_SHARED
142 #define __S011 PAGE_SHARED
143 #define __S100 PAGE_READONLY
144 #define __S101 PAGE_READONLY
145 #define __S110 PAGE_SHARED
146 #define __S111 PAGE_SHARED
147
148 #ifndef __ASSEMBLY__
149
150 extern pte_t __bad_page(void);
151
152 #define BAD_PAGE __bad_page()
153
154 extern unsigned long phys_base;
155
156 #define ZERO_PAGE(vaddr) (mem_map)
157
158 /* Warning: These take pointers to page structs now... */
159 #define mk_pte(page, pgprot) \
160 __pte((((page - mem_map) << PAGE_SHIFT)+phys_base) | pgprot_val(pgprot))
161 #define page_pte_prot(page, prot) mk_pte(page, prot)
162 #define page_pte(page) page_pte_prot(page, __pgprot(0))
163
164 #define mk_pte_phys(physpage, pgprot) (__pte((physpage) | pgprot_val(pgprot)))
165
166 extern inline pte_t pte_modify(pte_t orig_pte, pgprot_t new_prot)
167 {
168 pte_t __pte;
169
170 pte_val(__pte) = (pte_val(orig_pte) & _PAGE_CHG_MASK) |
171 pgprot_val(new_prot);
172
173 return __pte;
174 }
175 #define pmd_set(pmdp, ptep) \
176 (pmd_val(*(pmdp)) = (__pa((unsigned long) (ptep)) >> 11UL))
177 #define pgd_set(pgdp, pmdp) \
178 (pgd_val(*(pgdp)) = (__pa((unsigned long) (pmdp)) >> 11UL))
179 #define pmd_page(pmd) ((unsigned long) __va((pmd_val(pmd)<<11UL)))
180 #define pgd_page(pgd) ((unsigned long) __va((pgd_val(pgd)<<11UL)))
181 #define pte_none(pte) (!pte_val(pte))
182 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
183 #define pte_clear(pte) (pte_val(*(pte)) = 0UL)
184 #define pmd_none(pmd) (!pmd_val(pmd))
185 #define pmd_bad(pmd) (0)
186 #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
187 #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
188 #define pgd_none(pgd) (!pgd_val(pgd))
189 #define pgd_bad(pgd) (0)
190 #define pgd_present(pgd) (pgd_val(pgd) != 0UL)
191 #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL)
192
193 /* The following only work if pte_present() is true.
194 * Undefined behaviour if not..
195 */
196 #define pte_read(pte) (pte_val(pte) & _PAGE_READ)
197 #define pte_exec(pte) pte_read(pte)
198 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
199 #define pte_dirty(pte) (pte_val(pte) & _PAGE_MODIFIED)
200 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
201 #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~(_PAGE_WRITE|_PAGE_W)))
202 #define pte_rdprotect(pte) (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_READ))
203 #define pte_mkclean(pte) (__pte(pte_val(pte) & ~(_PAGE_MODIFIED|_PAGE_W)))
204 #define pte_mkold(pte) (__pte(((pte_val(pte)<<1UL)>>1UL) & ~_PAGE_ACCESSED))
205
206 /* Permanent address of a page. */
207 #define __page_address(page) ((page)->virtual)
208 #define page_address(page) ({ __page_address(page); })
209
210 #define pte_page(x) (mem_map+(((pte_val(x)&_PAGE_PADDR)-phys_base)>>PAGE_SHIFT))
211
212 /* Be very careful when you change these three, they are delicate. */
213 #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_ACCESSED | _PAGE_R))
214 #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_WRITE))
215 #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_MODIFIED | _PAGE_W))
216
217 /* to find an entry in a page-table-directory. */
218 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD))
219 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
220
221 /* to find an entry in a kernel page-table-directory */
222 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
223
224 /* Find an entry in the second-level page table.. */
225 #define pmd_offset(dir, address) ((pmd_t *) pgd_page(*(dir)) + \
226 ((address >> PMD_SHIFT) & (REAL_PTRS_PER_PMD-1)))
227
228 /* Find an entry in the third-level page table.. */
229 #define pte_offset(dir, address) ((pte_t *) pmd_page(*(dir)) + \
230 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
231
232 extern pgd_t swapper_pg_dir[1];
233
234 /* These do nothing with the way I have things setup. */
235 #define mmu_lockarea(vaddr, len) (vaddr)
236 #define mmu_unlockarea(vaddr, len) do { } while(0)
237
238 extern void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t);
239
240 #define flush_icache_page(vma, pg) do { } while(0)
241
242 /* Make a non-present pseudo-TTE. */
243 extern inline pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space)
244 {
245 pte_t pte;
246 pte_val(pte) = ((page) | pgprot_val(prot) | _PAGE_E) & ~(unsigned long)_PAGE_CACHE;
247 pte_val(pte) |= (((unsigned long)space) << 32);
248 return pte;
249 }
250
251 /* Encode and de-code a swap entry */
252 #define SWP_TYPE(entry) (((entry).val >> PAGE_SHIFT) & 0xff)
253 #define SWP_OFFSET(entry) ((entry).val >> (PAGE_SHIFT + 8))
254 #define SWP_ENTRY(type, offset) \
255 ( (swp_entry_t) \
256 { \
257 ((type << PAGE_SHIFT) | (offset << (PAGE_SHIFT + 8))) \
258 } )
259 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
260 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
261
262 extern __inline__ unsigned long
263 sun4u_get_pte (unsigned long addr)
264 {
265 pgd_t *pgdp;
266 pmd_t *pmdp;
267 pte_t *ptep;
268
269 if (addr >= PAGE_OFFSET)
270 return addr & _PAGE_PADDR;
271 pgdp = pgd_offset_k (addr);
272 pmdp = pmd_offset (pgdp, addr);
273 ptep = pte_offset (pmdp, addr);
274 return pte_val (*ptep) & _PAGE_PADDR;
275 }
276
277 extern __inline__ unsigned long
278 __get_phys (unsigned long addr)
279 {
280 return sun4u_get_pte (addr);
281 }
282
283 extern __inline__ int
284 __get_iospace (unsigned long addr)
285 {
286 return ((sun4u_get_pte (addr) & 0xf0000000) >> 28);
287 }
288
289 extern unsigned long *sparc64_valid_addr_bitmap;
290
291 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
292 #define kern_addr_valid(addr) \
293 (test_bit(__pa((unsigned long)(addr))>>22, sparc64_valid_addr_bitmap))
294
295 extern int io_remap_page_range(unsigned long from, unsigned long offset,
296 unsigned long size, pgprot_t prot, int space);
297
298 #include <asm-generic/pgtable.h>
299
300 #endif /* !(__ASSEMBLY__) */
301
302 /* We provide our own get_unmapped_area to cope with VA holes for userland */
303 #define HAVE_ARCH_UNMAPPED_AREA
304
305 #endif /* !(_SPARC64_PGTABLE_H) */
306
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