1 /* $Id: sab82532.h,v 1.6 2000/04/13 07:22:35 ecd Exp $
2 * sab82532.h: Register Definitions for the Siemens SAB82532 DUSCC
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 */
6
7 #ifndef _SPARC64_SAB82532_H
8 #define _SPARC64_SAB82532_H
9
10 #include <linux/types.h>
11 #include <linux/serial.h>
12
13 struct sab82532_async_rd_regs {
14 u8 rfifo[0x20]; /* Receive FIFO */
15 u8 star; /* Status Register */
16 u8 __pad1;
17 u8 mode; /* Mode Register */
18 u8 timr; /* Timer Register */
19 u8 xon; /* XON Character */
20 u8 xoff; /* XOFF Character */
21 u8 tcr; /* Termination Character Register */
22 u8 dafo; /* Data Format */
23 u8 rfc; /* RFIFO Control Register */
24 u8 __pad2;
25 u8 rbcl; /* Receive Byte Count Low */
26 u8 rbch; /* Receive Byte Count High */
27 u8 ccr0; /* Channel Configuration Register 0 */
28 u8 ccr1; /* Channel Configuration Register 1 */
29 u8 ccr2; /* Channel Configuration Register 2 */
30 u8 ccr3; /* Channel Configuration Register 3 */
31 u8 __pad3[4];
32 u8 vstr; /* Version Status Register */
33 u8 __pad4[3];
34 u8 gis; /* Global Interrupt Status */
35 u8 ipc; /* Interrupt Port Configuration */
36 u8 isr0; /* Interrupt Status 0 */
37 u8 isr1; /* Interrupt Status 1 */
38 u8 pvr; /* Port Value Register */
39 u8 pis; /* Port Interrupt Status */
40 u8 pcr; /* Port Configuration Register */
41 u8 ccr4; /* Channel Configuration Register 4 */
42 };
43
44 struct sab82532_async_wr_regs {
45 u8 xfifo[0x20]; /* Transmit FIFO */
46 u8 cmdr; /* Command Register */
47 u8 __pad1;
48 u8 mode;
49 u8 timr;
50 u8 xon;
51 u8 xoff;
52 u8 tcr;
53 u8 dafo;
54 u8 rfc;
55 u8 __pad2;
56 u8 xbcl; /* Transmit Byte Count Low */
57 u8 xbch; /* Transmit Byte Count High */
58 u8 ccr0;
59 u8 ccr1;
60 u8 ccr2;
61 u8 ccr3;
62 u8 tsax; /* Time-Slot Assignment Reg. Transmit */
63 u8 tsar; /* Time-Slot Assignment Reg. Receive */
64 u8 xccr; /* Transmit Channel Capacity Register */
65 u8 rccr; /* Receive Channel Capacity Register */
66 u8 bgr; /* Baud Rate Generator Register */
67 u8 tic; /* Transmit Immediate Character */
68 u8 mxn; /* Mask XON Character */
69 u8 mxf; /* Mask XOFF Character */
70 u8 iva; /* Interrupt Vector Address */
71 u8 ipc;
72 u8 imr0; /* Interrupt Mask Register 0 */
73 u8 imr1; /* Interrupt Mask Register 1 */
74 u8 pvr;
75 u8 pim; /* Port Interrupt Mask */
76 u8 pcr;
77 u8 ccr4;
78 };
79
80 struct sab82532_async_rw_regs { /* Read/Write registers */
81 u8 __pad1[0x20];
82 u8 __pad2;
83 u8 __pad3;
84 u8 mode;
85 u8 timr;
86 u8 xon;
87 u8 xoff;
88 u8 tcr;
89 u8 dafo;
90 u8 rfc;
91 u8 __pad4;
92 u8 __pad5;
93 u8 __pad6;
94 u8 ccr0;
95 u8 ccr1;
96 u8 ccr2;
97 u8 ccr3;
98 u8 __pad7;
99 u8 __pad8;
100 u8 __pad9;
101 u8 __pad10;
102 u8 __pad11;
103 u8 __pad12;
104 u8 __pad13;
105 u8 __pad14;
106 u8 __pad15;
107 u8 ipc;
108 u8 __pad16;
109 u8 __pad17;
110 u8 pvr;
111 u8 __pad18;
112 u8 pcr;
113 u8 ccr4;
114 };
115
116 union sab82532_async_regs {
117 __volatile__ struct sab82532_async_rd_regs r;
118 __volatile__ struct sab82532_async_wr_regs w;
119 __volatile__ struct sab82532_async_rw_regs rw;
120 };
121
122 #define NR_PORTS 2
123
124 union sab82532_irq_status {
125 unsigned short stat;
126 struct {
127 unsigned char isr0;
128 unsigned char isr1;
129 } sreg;
130 };
131
132 struct sab82532 {
133 int magic;
134 int baud_base;
135 union sab82532_async_regs *regs;
136 int irq;
137 int flags; /* defined in tty.h */
138 int type; /* SAB82532 version */
139 struct tty_struct *tty;
140 int read_status_mask;
141 int ignore_status_mask;
142 int timeout;
143 int xmit_fifo_size;
144 int recv_fifo_size;
145 int custom_divisor;
146 int baud;
147 unsigned int cec_timeout;
148 unsigned int tec_timeout;
149 int x_char;
150 int close_delay;
151 unsigned short closing_wait;
152 unsigned short closing_wait2;
153 int all_sent;
154 int is_console;
155 unsigned char interrupt_mask0;
156 unsigned char interrupt_mask1;
157 unsigned char pvr_dtr_bit;
158 unsigned char pvr_dsr_bit;
159 unsigned char dcd;
160 unsigned char cts;
161 unsigned char dsr;
162 unsigned long event;
163 unsigned long last_active;
164 int line;
165 int count;
166 int blocked_open;
167 long session;
168 long pgrp;
169 unsigned char *xmit_buf;
170 int xmit_head;
171 int xmit_tail;
172 int xmit_cnt;
173 struct tq_struct tqueue;
174 struct tq_struct tqueue_hangup;
175 struct async_icount icount;
176 struct termios normal_termios;
177 struct termios callout_termios;
178 wait_queue_head_t open_wait;
179 wait_queue_head_t close_wait;
180 wait_queue_head_t delta_msr_wait;
181 struct sab82532 *next;
182 struct sab82532 *prev;
183 };
184
185
186 /* RFIFO Status Byte */
187 #define SAB82532_RSTAT_PE 0x80
188 #define SAB82532_RSTAT_FE 0x40
189 #define SAB82532_RSTAT_PARITY 0x01
190
191 /* Status Register (STAR) */
192 #define SAB82532_STAR_XDOV 0x80
193 #define SAB82532_STAR_XFW 0x40
194 #define SAB82532_STAR_RFNE 0x20
195 #define SAB82532_STAR_FCS 0x10
196 #define SAB82532_STAR_TEC 0x08
197 #define SAB82532_STAR_CEC 0x04
198 #define SAB82532_STAR_CTS 0x02
199
200 /* Command Register (CMDR) */
201 #define SAB82532_CMDR_RMC 0x80
202 #define SAB82532_CMDR_RRES 0x40
203 #define SAB82532_CMDR_RFRD 0x20
204 #define SAB82532_CMDR_STI 0x10
205 #define SAB82532_CMDR_XF 0x08
206 #define SAB82532_CMDR_XRES 0x01
207
208 /* Mode Register (MODE) */
209 #define SAB82532_MODE_FRTS 0x40
210 #define SAB82532_MODE_FCTS 0x20
211 #define SAB82532_MODE_FLON 0x10
212 #define SAB82532_MODE_RAC 0x08
213 #define SAB82532_MODE_RTS 0x04
214 #define SAB82532_MODE_TRS 0x02
215 #define SAB82532_MODE_TLP 0x01
216
217 /* Timer Register (TIMR) */
218 #define SAB82532_TIMR_CNT_MASK 0xe0
219 #define SAB82532_TIMR_VALUE_MASK 0x1f
220
221 /* Data Format (DAFO) */
222 #define SAB82532_DAFO_XBRK 0x40
223 #define SAB82532_DAFO_STOP 0x20
224 #define SAB82532_DAFO_PAR_SPACE 0x00
225 #define SAB82532_DAFO_PAR_ODD 0x08
226 #define SAB82532_DAFO_PAR_EVEN 0x10
227 #define SAB82532_DAFO_PAR_MARK 0x18
228 #define SAB82532_DAFO_PARE 0x04
229 #define SAB82532_DAFO_CHL8 0x00
230 #define SAB82532_DAFO_CHL7 0x01
231 #define SAB82532_DAFO_CHL6 0x02
232 #define SAB82532_DAFO_CHL5 0x03
233
234 /* RFIFO Control Register (RFC) */
235 #define SAB82532_RFC_DPS 0x40
236 #define SAB82532_RFC_DXS 0x20
237 #define SAB82532_RFC_RFDF 0x10
238 #define SAB82532_RFC_RFTH_1 0x00
239 #define SAB82532_RFC_RFTH_4 0x04
240 #define SAB82532_RFC_RFTH_16 0x08
241 #define SAB82532_RFC_RFTH_32 0x0c
242 #define SAB82532_RFC_TCDE 0x01
243
244 /* Received Byte Count High (RBCH) */
245 #define SAB82532_RBCH_DMA 0x80
246 #define SAB82532_RBCH_CAS 0x20
247
248 /* Transmit Byte Count High (XBCH) */
249 #define SAB82532_XBCH_DMA 0x80
250 #define SAB82532_XBCH_CAS 0x20
251 #define SAB82532_XBCH_XC 0x10
252
253 /* Channel Configuration Register 0 (CCR0) */
254 #define SAB82532_CCR0_PU 0x80
255 #define SAB82532_CCR0_MCE 0x40
256 #define SAB82532_CCR0_SC_NRZ 0x00
257 #define SAB82532_CCR0_SC_NRZI 0x08
258 #define SAB82532_CCR0_SC_FM0 0x10
259 #define SAB82532_CCR0_SC_FM1 0x14
260 #define SAB82532_CCR0_SC_MANCH 0x18
261 #define SAB82532_CCR0_SM_HDLC 0x00
262 #define SAB82532_CCR0_SM_SDLC_LOOP 0x01
263 #define SAB82532_CCR0_SM_BISYNC 0x02
264 #define SAB82532_CCR0_SM_ASYNC 0x03
265
266 /* Channel Configuration Register 1 (CCR1) */
267 #define SAB82532_CCR1_ODS 0x10
268 #define SAB82532_CCR1_BCR 0x08
269 #define SAB82532_CCR1_CM_MASK 0x07
270
271 /* Channel Configuration Register 2 (CCR2) */
272 #define SAB82532_CCR2_SOC1 0x80
273 #define SAB82532_CCR2_SOC0 0x40
274 #define SAB82532_CCR2_BR9 0x80
275 #define SAB82532_CCR2_BR8 0x40
276 #define SAB82532_CCR2_BDF 0x20
277 #define SAB82532_CCR2_SSEL 0x10
278 #define SAB82532_CCR2_XCS0 0x20
279 #define SAB82532_CCR2_RCS0 0x10
280 #define SAB82532_CCR2_TOE 0x08
281 #define SAB82532_CCR2_RWX 0x04
282 #define SAB82532_CCR2_DIV 0x01
283
284 /* Channel Configuration Register 3 (CCR3) */
285 #define SAB82532_CCR3_PSD 0x01
286
287 /* Time Slot Assignment Register Transmit (TSAX) */
288 #define SAB82532_TSAX_TSNX_MASK 0xfc
289 #define SAB82532_TSAX_XCS2 0x02 /* see also CCR2 */
290 #define SAB82532_TSAX_XCS1 0x01
291
292 /* Time Slot Assignment Register Receive (TSAR) */
293 #define SAB82532_TSAR_TSNR_MASK 0xfc
294 #define SAB82532_TSAR_RCS2 0x02 /* see also CCR2 */
295 #define SAB82532_TSAR_RCS1 0x01
296
297 /* Version Status Register (VSTR) */
298 #define SAB82532_VSTR_CD 0x80
299 #define SAB82532_VSTR_DPLA 0x40
300 #define SAB82532_VSTR_VN_MASK 0x0f
301 #define SAB82532_VSTR_VN_1 0x00
302 #define SAB82532_VSTR_VN_2 0x01
303 #define SAB82532_VSTR_VN_3_2 0x02
304
305 /* Global Interrupt Status Register (GIS) */
306 #define SAB82532_GIS_PI 0x80
307 #define SAB82532_GIS_ISA1 0x08
308 #define SAB82532_GIS_ISA0 0x04
309 #define SAB82532_GIS_ISB1 0x02
310 #define SAB82532_GIS_ISB0 0x01
311
312 /* Interrupt Vector Address (IVA) */
313 #define SAB82532_IVA_MASK 0xf1
314
315 /* Interrupt Port Configuration (IPC) */
316 #define SAB82532_IPC_VIS 0x80
317 #define SAB82532_IPC_SLA1 0x10
318 #define SAB82532_IPC_SLA0 0x08
319 #define SAB82532_IPC_CASM 0x04
320 #define SAB82532_IPC_IC_OPEN_DRAIN 0x00
321 #define SAB82532_IPC_IC_ACT_LOW 0x01
322 #define SAB82532_IPC_IC_ACT_HIGH 0x03
323
324 /* Interrupt Status Register 0 (ISR0) */
325 #define SAB82532_ISR0_TCD 0x80
326 #define SAB82532_ISR0_TIME 0x40
327 #define SAB82532_ISR0_PERR 0x20
328 #define SAB82532_ISR0_FERR 0x10
329 #define SAB82532_ISR0_PLLA 0x08
330 #define SAB82532_ISR0_CDSC 0x04
331 #define SAB82532_ISR0_RFO 0x02
332 #define SAB82532_ISR0_RPF 0x01
333
334 /* Interrupt Status Register 1 (ISR1) */
335 #define SAB82532_ISR1_BRK 0x80
336 #define SAB82532_ISR1_BRKT 0x40
337 #define SAB82532_ISR1_ALLS 0x20
338 #define SAB82532_ISR1_XOFF 0x10
339 #define SAB82532_ISR1_TIN 0x08
340 #define SAB82532_ISR1_CSC 0x04
341 #define SAB82532_ISR1_XON 0x02
342 #define SAB82532_ISR1_XPR 0x01
343
344 /* Interrupt Mask Register 0 (IMR0) */
345 #define SAB82532_IMR0_TCD 0x80
346 #define SAB82532_IMR0_TIME 0x40
347 #define SAB82532_IMR0_PERR 0x20
348 #define SAB82532_IMR0_FERR 0x10
349 #define SAB82532_IMR0_PLLA 0x08
350 #define SAB82532_IMR0_CDSC 0x04
351 #define SAB82532_IMR0_RFO 0x02
352 #define SAB82532_IMR0_RPF 0x01
353
354 /* Interrupt Mask Register 1 (IMR1) */
355 #define SAB82532_IMR1_BRK 0x80
356 #define SAB82532_IMR1_BRKT 0x40
357 #define SAB82532_IMR1_ALLS 0x20
358 #define SAB82532_IMR1_XOFF 0x10
359 #define SAB82532_IMR1_TIN 0x08
360 #define SAB82532_IMR1_CSC 0x04
361 #define SAB82532_IMR1_XON 0x02
362 #define SAB82532_IMR1_XPR 0x01
363
364 /* Port Interrupt Status Register (PIS) */
365 #define SAB82532_PIS_SYNC_B 0x08
366 #define SAB82532_PIS_DTR_B 0x04
367 #define SAB82532_PIS_DTR_A 0x02
368 #define SAB82532_PIS_SYNC_A 0x01
369
370 /* Channel Configuration Register 4 (CCR4) */
371 #define SAB82532_CCR4_MCK4 0x80
372 #define SAB82532_CCR4_EBRG 0x40
373 #define SAB82532_CCR4_TST1 0x20
374 #define SAB82532_CCR4_ICD 0x10
375
376
377 #endif /* !(_SPARC64_SAB82532_H) */
378
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