1 /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
2 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
3 * derived from Data Sheet, Copyright Motorola 1984 (!).
4 * It was written to be part of the Linux operating system.
5 */
6 /* permission is hereby granted to copy, modify and redistribute this code
7 * in terms of the GNU Library General Public License, Version 2 or later,
8 * at your option.
9 */
10
11 #ifndef _MC146818RTC_H
12 #define _MC146818RTC_H
13
14 #include <asm/io.h>
15 #include <linux/rtc.h> /* get the user-level API */
16 #include <asm/mc146818rtc.h> /* register access macros */
17
18 extern spinlock_t rtc_lock; /* serialize CMOS RAM access */
19
20 /**********************************************************************
21 * register summary
22 **********************************************************************/
23 #define RTC_SECONDS 0
24 #define RTC_SECONDS_ALARM 1
25 #define RTC_MINUTES 2
26 #define RTC_MINUTES_ALARM 3
27 #define RTC_HOURS 4
28 #define RTC_HOURS_ALARM 5
29 /* RTC_*_alarm is always true if 2 MSBs are set */
30 # define RTC_ALARM_DONT_CARE 0xC0
31
32 #define RTC_DAY_OF_WEEK 6
33 #define RTC_DAY_OF_MONTH 7
34 #define RTC_MONTH 8
35 #define RTC_YEAR 9
36
37 /* control registers - Moto names
38 */
39 #define RTC_REG_A 10
40 #define RTC_REG_B 11
41 #define RTC_REG_C 12
42 #define RTC_REG_D 13
43
44 /**********************************************************************
45 * register details
46 **********************************************************************/
47 #define RTC_FREQ_SELECT RTC_REG_A
48
49 /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus,
50 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
51 * totalling to a max high interval of 2.228 ms.
52 */
53 # define RTC_UIP 0x80
54 # define RTC_DIV_CTL 0x70
55 /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
56 # define RTC_REF_CLCK_4MHZ 0x00
57 # define RTC_REF_CLCK_1MHZ 0x10
58 # define RTC_REF_CLCK_32KHZ 0x20
59 /* 2 values for divider stage reset, others for "testing purposes only" */
60 # define RTC_DIV_RESET1 0x60
61 # define RTC_DIV_RESET2 0x70
62 /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
63 # define RTC_RATE_SELECT 0x0F
64
65 /**********************************************************************/
66 #define RTC_CONTROL RTC_REG_B
67 # define RTC_SET 0x80 /* disable updates for clock setting */
68 # define RTC_PIE 0x40 /* periodic interrupt enable */
69 # define RTC_AIE 0x20 /* alarm interrupt enable */
70 # define RTC_UIE 0x10 /* update-finished interrupt enable */
71 # define RTC_SQWE 0x08 /* enable square-wave output */
72 # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
73 # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
74 # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
75
76 /**********************************************************************/
77 #define RTC_INTR_FLAGS RTC_REG_C
78 /* caution - cleared by read */
79 # define RTC_IRQF 0x80 /* any of the following 3 is active */
80 # define RTC_PF 0x40
81 # define RTC_AF 0x20
82 # define RTC_UF 0x10
83
84 /**********************************************************************/
85 #define RTC_VALID RTC_REG_D
86 # define RTC_VRT 0x80 /* valid RAM and time */
87 /**********************************************************************/
88
89 /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY)
90 * determines if the following two #defines are needed
91 */
92 #ifndef BCD_TO_BIN
93 #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10)
94 #endif
95
96 #ifndef BIN_TO_BCD
97 #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10)
98 #endif
99
100 #endif /* _MC146818RTC_H */
101
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